EDA / VLSI CONCEPTS TEST QUESTIONS
AND ANSWERS
Net List - ANSWER List of properties and statistics usually for connection of
cells. There are different levels of net-list. ex: Gate level net-list
Standard Cell - ANSWER Cells are a combination of logic gates or standalone
gates.
Standard Cell Library - ANSWER A collection of all possible cells used in the
design of the chips entirety. The standard cells are created and provided by the
foundry to make place and route easier.
VDD and VSS - ANSWER VDD means the ground and VSS means the
voltage source. VSS and VDD can also be written as VCC and GND
respectively.
Power and Ground Lines - ANSWER Power and ground lines are VSS and
VDD. The lines are alternating and allow for set orientation of cells in a
uniform pattern.
DRC - ANSWER Design Rule Check: A check of geometry, orientation, and
spacing of wires and vias.
LVS - ANSWER Layout vs Schematic: A check of connectivity of the entire
system.
, VIA - ANSWER Via connections are alloy metals : usually varying depending
on metal properties. Used to connect different metal layers together.
ECO Fixing Violations When there are still violations after doing some
automatic rerouting, there are issues surrounding wire connectivity or geometry
that can only be fixed by humans. Using the place and route tools the engineer
can easily manually manipulate the wires to resolve the violations presented.
We call this an (Engineer Change Order)
Global Routing - ANSWER (Tile routing) The program runs algorithms that
roughly route the path the wire should take to make the connection through a
imaginary partitioned tile structure.
[Common Methods / Algorithms]
Sequential Global (Rip and Replace)
Concurrent Global Routing (0-1)
Steiner Trees (Shortest possible path via Steiner nodes)
Detailed Routing - ANSWER Using the global route given the placer tool can
now use its algorithm to place physical wires to represent the path taken. Paths
can extend through multiple metal layers and all of them are now represented
along with their vias.
Congestion Map - ANSWER These maps are very similar to heat maps. The
more wires there are the darker the color, ranging from blue to red. To more
simply put it, this map shows wire density. It can be used to show how many
possible connections are left in a certain region and whether or not one should
reroute or place wires elsewhere.
AND ANSWERS
Net List - ANSWER List of properties and statistics usually for connection of
cells. There are different levels of net-list. ex: Gate level net-list
Standard Cell - ANSWER Cells are a combination of logic gates or standalone
gates.
Standard Cell Library - ANSWER A collection of all possible cells used in the
design of the chips entirety. The standard cells are created and provided by the
foundry to make place and route easier.
VDD and VSS - ANSWER VDD means the ground and VSS means the
voltage source. VSS and VDD can also be written as VCC and GND
respectively.
Power and Ground Lines - ANSWER Power and ground lines are VSS and
VDD. The lines are alternating and allow for set orientation of cells in a
uniform pattern.
DRC - ANSWER Design Rule Check: A check of geometry, orientation, and
spacing of wires and vias.
LVS - ANSWER Layout vs Schematic: A check of connectivity of the entire
system.
, VIA - ANSWER Via connections are alloy metals : usually varying depending
on metal properties. Used to connect different metal layers together.
ECO Fixing Violations When there are still violations after doing some
automatic rerouting, there are issues surrounding wire connectivity or geometry
that can only be fixed by humans. Using the place and route tools the engineer
can easily manually manipulate the wires to resolve the violations presented.
We call this an (Engineer Change Order)
Global Routing - ANSWER (Tile routing) The program runs algorithms that
roughly route the path the wire should take to make the connection through a
imaginary partitioned tile structure.
[Common Methods / Algorithms]
Sequential Global (Rip and Replace)
Concurrent Global Routing (0-1)
Steiner Trees (Shortest possible path via Steiner nodes)
Detailed Routing - ANSWER Using the global route given the placer tool can
now use its algorithm to place physical wires to represent the path taken. Paths
can extend through multiple metal layers and all of them are now represented
along with their vias.
Congestion Map - ANSWER These maps are very similar to heat maps. The
more wires there are the darker the color, ranging from blue to red. To more
simply put it, this map shows wire density. It can be used to show how many
possible connections are left in a certain region and whether or not one should
reroute or place wires elsewhere.
