COMPUTER SCIENCE PAPER 1STUDY
QUESTIONS AND ANSWERS
Control Unit - CORRECT ANSWER-A register in the cpu that
controls and coordinates the activities of the cpu directing the
flow of data
Bus - CORRECT ANSWER-a series of connectors that transfer
signals between internal components
Memory Read - CORRECT ANSWER-causes data from the
addressed location in RAM to be placed on the data bus
Memory Write - CORRECT ANSWER-Causes data on the data
bus to be written into the addressed location.
Bus Request - CORRECT ANSWER-Indicates that a device is
requesting the use of the data bus
Bus Grant - CORRECT ANSWER-Indicates that the CPU has
granted access to the data bus.
System bus - CORRECT ANSWER-collective term for address,
data and control bus
Data bus - CORRECT ANSWER-A bi-directional path for
moving data and instructions between system components
Clock - CORRECT ANSWER-used to synchronize operations
,Control bus - CORRECT ANSWER-A bi-directional bus to
transmit command, timing and specific status information
between system components
Address bus - CORRECT ANSWER-A one directional bus that
transmits memory addresses that are used as operands in
programming instructions, so that data can be retrieved from
main memory
ALU - CORRECT ANSWER-Arithmetic-Logic unit, preforms
logical and arithmetic operations on data
e.g. ADD, SUBTRACT, shift operations or Boolean logic
Registers - CORRECT ANSWER-High speed memory cells, all
arithmetic and logic happens in these, typically there are 16
general purpose registers in a CPU, they are very fast
Accumulator - CORRECT ANSWER-A special purpose register
which stores the result of calculations made by the ALU
Program Counter (PC) - CORRECT ANSWER-Holds the
address of the next instruction to be executed, this can be the
next instruction in a sequence of instructions, or a branch/ jump
Current instruction register (CIR) - CORRECT ANSWER-stores
the actual instruction that is being decoded
Memory address register (MAR) - CORRECT ANSWER-stores
the address of instructions and data that need to be fetched
from or sent to memory
Memory data register (MDR) - CORRECT ANSWER-stores the
data which is to be sent or fetched from memory
Interrupt registers - CORRECT ANSWER-generates and
detects interrupts
,Fetch Decode Execute register sequence - CORRECT
ANSWER-PC
MAR
Address Bus
Memory
Data bus
MDR
CIR
Decode Unit
MAR
Address Bus
Main Memory
Fetch phase - CORRECT ANSWER-- Instructions pulled from
memory and stored in main memory.
- Program Counter (a register) stores the address location of
the instruction
- Program Counter and instructions are placed in the Instruction
Register (IR)
- Program Counter is incremented by 1
Decode phase - CORRECT ANSWER-1. Instruction in CIR is
decoded
2. Instruction is split into opcode and operand
3. the operand determines the type of instruction
- if its the address of the data used with the operation it is
copied into the MAR
- if it the actual data to be operated on it is copied into the MDR
4. the data to be operated on is passed into the ALU/ acc
Execute phase - CORRECT ANSWER-The appropriate
instruction/ opcode is carried out on the data/ operand
Main factors affecting preformance - CORRECT ANSWER--
Clock speed
- Number of cores
, - The amount and type of cache
Clock speed - CORRECT ANSWER-The system clock
generates a series of signals (1 or 0) synchronising with the
CPU operations. The CPU cannot preform faster than the
system clock.
Positives of increasing clock speed - CORRECT ANSWER-You
can carry out more instructions in a given time; improved
performance
What is clock speed measured in? - CORRECT ANSWER-Hz
Negatives of increasing clock speed - CORRECT ANSWER-
more heat generated meaning computers must be cooled
(either with heat sync/fan or water/oil cooling)
Positive of multiple cores - CORRECT ANSWER-may speed
processing as concurrency is available
negatives of multiple cores - CORRECT ANSWER-complicated
circuitry (more expensive)
doesn't always improve performance
Positives of increasing cache size - CORRECT ANSWER-less
time fetching data; improved performance
Negatives of increasing cache size - CORRECT ANSWER-
expensive, physically further from cpu and thus slower
Level 1 cache - CORRECT ANSWER-Small but extremely fast
Level 2 cache - CORRECT ANSWER-fairly fast and medium
sized
Level 3 cache - CORRECT ANSWER-slower and bigger
QUESTIONS AND ANSWERS
Control Unit - CORRECT ANSWER-A register in the cpu that
controls and coordinates the activities of the cpu directing the
flow of data
Bus - CORRECT ANSWER-a series of connectors that transfer
signals between internal components
Memory Read - CORRECT ANSWER-causes data from the
addressed location in RAM to be placed on the data bus
Memory Write - CORRECT ANSWER-Causes data on the data
bus to be written into the addressed location.
Bus Request - CORRECT ANSWER-Indicates that a device is
requesting the use of the data bus
Bus Grant - CORRECT ANSWER-Indicates that the CPU has
granted access to the data bus.
System bus - CORRECT ANSWER-collective term for address,
data and control bus
Data bus - CORRECT ANSWER-A bi-directional path for
moving data and instructions between system components
Clock - CORRECT ANSWER-used to synchronize operations
,Control bus - CORRECT ANSWER-A bi-directional bus to
transmit command, timing and specific status information
between system components
Address bus - CORRECT ANSWER-A one directional bus that
transmits memory addresses that are used as operands in
programming instructions, so that data can be retrieved from
main memory
ALU - CORRECT ANSWER-Arithmetic-Logic unit, preforms
logical and arithmetic operations on data
e.g. ADD, SUBTRACT, shift operations or Boolean logic
Registers - CORRECT ANSWER-High speed memory cells, all
arithmetic and logic happens in these, typically there are 16
general purpose registers in a CPU, they are very fast
Accumulator - CORRECT ANSWER-A special purpose register
which stores the result of calculations made by the ALU
Program Counter (PC) - CORRECT ANSWER-Holds the
address of the next instruction to be executed, this can be the
next instruction in a sequence of instructions, or a branch/ jump
Current instruction register (CIR) - CORRECT ANSWER-stores
the actual instruction that is being decoded
Memory address register (MAR) - CORRECT ANSWER-stores
the address of instructions and data that need to be fetched
from or sent to memory
Memory data register (MDR) - CORRECT ANSWER-stores the
data which is to be sent or fetched from memory
Interrupt registers - CORRECT ANSWER-generates and
detects interrupts
,Fetch Decode Execute register sequence - CORRECT
ANSWER-PC
MAR
Address Bus
Memory
Data bus
MDR
CIR
Decode Unit
MAR
Address Bus
Main Memory
Fetch phase - CORRECT ANSWER-- Instructions pulled from
memory and stored in main memory.
- Program Counter (a register) stores the address location of
the instruction
- Program Counter and instructions are placed in the Instruction
Register (IR)
- Program Counter is incremented by 1
Decode phase - CORRECT ANSWER-1. Instruction in CIR is
decoded
2. Instruction is split into opcode and operand
3. the operand determines the type of instruction
- if its the address of the data used with the operation it is
copied into the MAR
- if it the actual data to be operated on it is copied into the MDR
4. the data to be operated on is passed into the ALU/ acc
Execute phase - CORRECT ANSWER-The appropriate
instruction/ opcode is carried out on the data/ operand
Main factors affecting preformance - CORRECT ANSWER--
Clock speed
- Number of cores
, - The amount and type of cache
Clock speed - CORRECT ANSWER-The system clock
generates a series of signals (1 or 0) synchronising with the
CPU operations. The CPU cannot preform faster than the
system clock.
Positives of increasing clock speed - CORRECT ANSWER-You
can carry out more instructions in a given time; improved
performance
What is clock speed measured in? - CORRECT ANSWER-Hz
Negatives of increasing clock speed - CORRECT ANSWER-
more heat generated meaning computers must be cooled
(either with heat sync/fan or water/oil cooling)
Positive of multiple cores - CORRECT ANSWER-may speed
processing as concurrency is available
negatives of multiple cores - CORRECT ANSWER-complicated
circuitry (more expensive)
doesn't always improve performance
Positives of increasing cache size - CORRECT ANSWER-less
time fetching data; improved performance
Negatives of increasing cache size - CORRECT ANSWER-
expensive, physically further from cpu and thus slower
Level 1 cache - CORRECT ANSWER-Small but extremely fast
Level 2 cache - CORRECT ANSWER-fairly fast and medium
sized
Level 3 cache - CORRECT ANSWER-slower and bigger
