DSA TLP
What is TLP - answer
Data level parallelism - answer Different data, same instructions - as if the data can be
made to flow through parallel paths. SIMD, energy efficient.
Convoy - answer A set of vector instructions that could potentially execute together -
instruction level parallelism extracted from vector instructions
Vector execution time - answer Depends on 3 factors
1. length of the operand vectors
2. structural hazards
3. data dependencies
VMIPS functional units consume one element per clk cycle, so execution time is approx.
the vector length - just factor 1
Chaining of vector operations - answer Allows a vector operation to start as soon as the
individual elements of its vector source operand become available. Similar to the
concept of data forwarding/ bypassing - overlapping actions on different elements, not
penalized by having to wait for entire vector
Chime - answer Unit of time to execute 1 convoy of instructions
Vector operation using pipelined FUs - answer Instead of 1 FU generating result
elements 0-63, 4 FUs pipelined can work parallelly, with the first one providing 0, 4, 8...
the next providing 1,5,9, etc
What if vector length not known at compile time - answer Use Vector Length Register
VLR, write code to work on less than or equal to Maximum vector length (MVL) - then
use n/MVL to truncate operations to an n length vector
if-conversion - answer Turning branches into conditionally executed instructions by a
vector mask. Vector operations become NOPs where the mask bit is 0, or occur where
the mask bit is 1.
SIMD extensions in CPU concept - answer ISA in CPUs updated to provide SIMD
functionality by recognizing that media applications operate on data types narrower than
the native word size. Operands must be consecutive and aligned memory locations, e.g.
disconnecting carry chains to partition adder to leverage sub word data parallelism.
Limitations of SIMD in CPU - answer1. no vector masking capability
What is TLP - answer
Data level parallelism - answer Different data, same instructions - as if the data can be
made to flow through parallel paths. SIMD, energy efficient.
Convoy - answer A set of vector instructions that could potentially execute together -
instruction level parallelism extracted from vector instructions
Vector execution time - answer Depends on 3 factors
1. length of the operand vectors
2. structural hazards
3. data dependencies
VMIPS functional units consume one element per clk cycle, so execution time is approx.
the vector length - just factor 1
Chaining of vector operations - answer Allows a vector operation to start as soon as the
individual elements of its vector source operand become available. Similar to the
concept of data forwarding/ bypassing - overlapping actions on different elements, not
penalized by having to wait for entire vector
Chime - answer Unit of time to execute 1 convoy of instructions
Vector operation using pipelined FUs - answer Instead of 1 FU generating result
elements 0-63, 4 FUs pipelined can work parallelly, with the first one providing 0, 4, 8...
the next providing 1,5,9, etc
What if vector length not known at compile time - answer Use Vector Length Register
VLR, write code to work on less than or equal to Maximum vector length (MVL) - then
use n/MVL to truncate operations to an n length vector
if-conversion - answer Turning branches into conditionally executed instructions by a
vector mask. Vector operations become NOPs where the mask bit is 0, or occur where
the mask bit is 1.
SIMD extensions in CPU concept - answer ISA in CPUs updated to provide SIMD
functionality by recognizing that media applications operate on data types narrower than
the native word size. Operands must be consecutive and aligned memory locations, e.g.
disconnecting carry chains to partition adder to leverage sub word data parallelism.
Limitations of SIMD in CPU - answer1. no vector masking capability
