8-Bit Arithmetic Logic Unit

T HE ECE 547 VLSI design project described in this paper is an 8-bit Arithmetic Logic Unit (ALU). We used the 74S181 [1] 4-bit ALU design, which was manufactured by Texas Instruments, as the base of the 8-bit design. Our ALU takes two 8-bits inputs busses (A and B) and performs 32 arithmetic functions and 16 logic functions. There is a 4-bit function select bus (S) to choose the specific operation to perform on the inputs. Also the ALU has one carry input (Cin). The function select M is called the Mode selector. When M is high, the operation is a logic function; when M is low, an arithmetic operation is indicated. The carry input can affect the output produced for arithmetic functions. The output is one 8-bit bus (F) and one carry out (Cout). The carry output Cout tells us whether a carry has occurred by operation performed. The speed of the ALU was not a design consideration. However, after simulation with extracted parasitics we realized that it could run up to approximately 50MHz. The ALU ran at low power equal to 78.9 mW RMS at 5 volts (at 50 MHz). The final layout was implemented through MOSIS, with AMI’s C5N process. We used the 0.6 m minimum gate length technology. The device is packaged in a 40-pin ceramic DIP. B. Objectives Because ALUs can be built in so many ways with wide specifications and since the objective of the class project is to learn the basic of VLSI design, the specifications of the ALU were relaxed. The main objective of the project is to have a working ALU that performs different arithmetic and logic functions for all possible combinations of the inputs. The speed of ALU was not an issue and we wanted it to run at low power. II. CIRCUIT DESIGN This chapter gives an overview of the Hierarchy of the 8-bit ALU and its design. First, we will introduce all the different types of logic gates that has been used in the design. Then, we will give an overview of the 4-bit ALU, 74S181 [1] and show how we broke down the original design of Texas Instruments into different blocks to facilitate the layout task later on. Finally, we will discuss the top level of the design and show how we combined three 4-bit ALU with five multiplexers in such manner to obtain our 8-bit ALU. A. Logic Gates We used the CMOS technology to build our gates. From the lowest level NMOS and PMOS, we designed the logic gates needed to form the different blocks of our 4-bit ALU. We used standard designs for logic gates with different possible pull-up and pull-down networks depending on the logic we want to perform. We used the minimum sizing for all the transistors with channel width and length are related as follow: • Wp/Lp=3/0.6 for PMOS • Wn/Lp=1.5/0.6 for PMOS However, when the logic circuit had more than one possible pull-up (or pull-down) current path, we had to follow the general digital design rules for sizing based on the idea of ”worst case”. All the AND gates are NAND gates with inverters. Furthermore, we built a pass gate that we used for multiplexer design. All our logic gates were symmetrical with low power dissipation. The types of logic gates used in the design are as follow: • Digital Output Buffer • Inverter • 2,3,4 and 5 input AND • 2,3,4 and 5 input NAND • 2,3,and 4 input NOR • 2 input XOR • PASS Transistor See Table I for a listing of the various logic g