Verilog
Revision Guide
March 1, 2024
1 Introduction
This revision guide provides an overview of essential Verilog concepts.
2 Data Types
1 // Declaring variables
2 reg [7:0] data ; // 8 - bit register
3 wire [3:0] address ; // 4 - bit wire
4 parameter WIDTH = 8; // Parameter declaration
5
6 // Data types
7 logic // Can represent 4 - state values
8 integer // 32 - bit signed integer
9 real // Floating - point number
3 Control Structures
1 // Conditional statements
2 if ( condition ) begin
3 // Code block
4 end else begin
5 // Code block
6 end
7
8 // Case statement
9 case ( selector )
10 2 ’ b00 : // Code block
11 2 ’ b01 : // Code block
12 default : // Code block
13 endcase
4 Sequential Logic
1 // Always block
2 always @ ( posedge clk ) begin
3 // Code block
4 end
5
6 // Non - blocking assignment
7 always @ ( posedge clk ) begin
8 q <= d ;
9 end
1
Revision Guide
March 1, 2024
1 Introduction
This revision guide provides an overview of essential Verilog concepts.
2 Data Types
1 // Declaring variables
2 reg [7:0] data ; // 8 - bit register
3 wire [3:0] address ; // 4 - bit wire
4 parameter WIDTH = 8; // Parameter declaration
5
6 // Data types
7 logic // Can represent 4 - state values
8 integer // 32 - bit signed integer
9 real // Floating - point number
3 Control Structures
1 // Conditional statements
2 if ( condition ) begin
3 // Code block
4 end else begin
5 // Code block
6 end
7
8 // Case statement
9 case ( selector )
10 2 ’ b00 : // Code block
11 2 ’ b01 : // Code block
12 default : // Code block
13 endcase
4 Sequential Logic
1 // Always block
2 always @ ( posedge clk ) begin
3 // Code block
4 end
5
6 // Non - blocking assignment
7 always @ ( posedge clk ) begin
8 q <= d ;
9 end
1
