Aslevel
OCR
Oxford Cambridge and RSA
GCE
Computer Science
H046/01: Computing principles
AS Level
Mark Scheme for June 2023
,Aslevel
OCR (Oxford Cambridge and RSA) is a leading UK awarding body, providing a wide
range of qualifications to meet the needs of candidates of all ages and abilities. OCR
qualifications include AS/A Levels, Diplomas, GCSEs, Cambridge Nationals,
Cambridge Technicals, Functional Skills, Key Skills, Entry Level qualifications, NVQs
and vocational qualifications in areas such as IT, business, languages,
teaching/training, administration and secretarial skills.
It is also responsible for developing new specifications to meet national
requirements and the needs of students and teachers. OCR is a not-for-profit
organisation; any surplus made is invested back into the establishment to help
towards the development of qualifications and support, which keep pace with the
changing needs of today’s society.
This mark scheme is published as an aid to teachers and students, to indicate the
requirements of the examination. It shows the basis on which marks were awarded
by examiners. It does not indicate the details of the discussions which took place at
an examiners’ meeting before marking commenced.
All examiners are instructed that alternative correct answers and unexpected
approaches in candidates’ scripts must be given marks that fairly reflect the
relevant knowledge and skills demonstrated.
Mark schemes should be read in conjunction with the published question papers
and the report on the examination.
© OCR 2023
, MARKING INSTRUCTIONS
Question Answer Mark Guidance
1 (a) Clock Speed … AO1. One mark for stating the factor, mark for
1 expanding the factor
… The speed at which the fetch decode (2)
execute cycle is completed/ the speed a AO1. - Accept cycles for “FDE Cycles”
single core can execute instructions 2 (2)
Number of cores/ independent processing
units
…
…that can fetch decode execute at the
same
time
Cache size…
… memory that contains
recently/frequently
used instructions/data
…memory that has a faster R/W speed
than
RAM
…memory that is closer to/onboard the
CPU
1 (b) CISC has a larger instruction set AO1. Accept any other valid points
RISC has a smaller instruction set 2
(2) Mark in pairs
CISC is difficult to pipeline
RISC is easier to pipeline
CISC tends to have more addressing
modes
RISC tends to have fewer addressing
modes
OCR
Oxford Cambridge and RSA
GCE
Computer Science
H046/01: Computing principles
AS Level
Mark Scheme for June 2023
,Aslevel
OCR (Oxford Cambridge and RSA) is a leading UK awarding body, providing a wide
range of qualifications to meet the needs of candidates of all ages and abilities. OCR
qualifications include AS/A Levels, Diplomas, GCSEs, Cambridge Nationals,
Cambridge Technicals, Functional Skills, Key Skills, Entry Level qualifications, NVQs
and vocational qualifications in areas such as IT, business, languages,
teaching/training, administration and secretarial skills.
It is also responsible for developing new specifications to meet national
requirements and the needs of students and teachers. OCR is a not-for-profit
organisation; any surplus made is invested back into the establishment to help
towards the development of qualifications and support, which keep pace with the
changing needs of today’s society.
This mark scheme is published as an aid to teachers and students, to indicate the
requirements of the examination. It shows the basis on which marks were awarded
by examiners. It does not indicate the details of the discussions which took place at
an examiners’ meeting before marking commenced.
All examiners are instructed that alternative correct answers and unexpected
approaches in candidates’ scripts must be given marks that fairly reflect the
relevant knowledge and skills demonstrated.
Mark schemes should be read in conjunction with the published question papers
and the report on the examination.
© OCR 2023
, MARKING INSTRUCTIONS
Question Answer Mark Guidance
1 (a) Clock Speed … AO1. One mark for stating the factor, mark for
1 expanding the factor
… The speed at which the fetch decode (2)
execute cycle is completed/ the speed a AO1. - Accept cycles for “FDE Cycles”
single core can execute instructions 2 (2)
Number of cores/ independent processing
units
…
…that can fetch decode execute at the
same
time
Cache size…
… memory that contains
recently/frequently
used instructions/data
…memory that has a faster R/W speed
than
RAM
…memory that is closer to/onboard the
CPU
1 (b) CISC has a larger instruction set AO1. Accept any other valid points
RISC has a smaller instruction set 2
(2) Mark in pairs
CISC is difficult to pipeline
RISC is easier to pipeline
CISC tends to have more addressing
modes
RISC tends to have fewer addressing
modes
