WGU C952
LATEST ACTUAL EXAM WITH VERIFIED QUESTIONS &
CORRECT ANSWERS
Question 1.
A technique to get more performance from loops that access arrays, in which multiple copies of the
loop body are made and instructions from different iterations are scheduled together.
ANSWER
loop unrolling
Question 2.
The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to
memory or a register.
ANSWER
Reorder Buffer
Question 3.
An address that corresponds to a location in virtual space and is translated by address mapping to a
physical address when memory is accessed.
ANSWER
virtual address
Question 4.
A uniprocessor
ANSWER
Single Instruction Single Data (SISD)
,Question 5.
the 4-bit ALU control input using a small control unit that has as inputs the opcode field of the
instruction and a 2-bit control field
indicates whether the operation to be performed should be add (00) for loads and stores, pass input b
(01) for CBZ, or be determined by the operation encoded in the opcode field (10)
10 is ORR, AND, SUB, ADD (R-type)
00 is LDUR, STUR
01 is CBZ
ANSWER
ALUOp
Question 6.
data transfer instruction that copies data from memory to a register
ANSWER
load
Question 7.
The part of the computer architecture related to programming, including the native data types,
instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and
external I/O.
ANSWER
Instruction Set Architecture (ISA)
Question 8.
Programming language that has the same structure and set of commands as machine languages but
allows programmers to use symbolic representations of numeric machine code.
ANSWER
Assembly Language
,Question 9.
The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the
result of an operation to programmer-visible registers and memory.
ANSWER
commit unit
Question 10.
The fraction of memory accesses not found in a level of the memory hierarchy
ANSWER
Miss rate
Question 11.
An on/off switch controlled by an electric signal
ANSWER
Transistor
Question 12.
Nonvolatile memory used to store programs and data between runs; typically consists of flash
memory in PMDs and magnetic disks in servers.
ANSWER
Secondary memory
Question 13.
the amount of work performed by a system during a given period of time
ANSWER
throughput
, Question 14.
A branch predictor that combines local behavior of a particular branch and global information about
the behavior of some recent number of executed branches.
ANSWER
Correlating predictor
Question 15.
The unpopularity of imprecise interrupts led to the standard of commit units in dynamically scheduled
pipelined processors
ANSWER
Imprecise interupt
Question 16.
A technique that uses main memory as a "cache" for secondary storage
The address is broken into a virtual page number and a page offset
ANSWER
virtual memory
Question 17.
The principle stating that if a data location is referenced, data locations with nearby addresses will
tend to be referenced soon.
ANSWER
spatial locality
Question 18.
A structure that caches the destination PC or destination instruction for a branch. It is usually
organized as a cache with tags, making it more costly than a simple prediction buffer.
ANSWER
Branch target buffer
LATEST ACTUAL EXAM WITH VERIFIED QUESTIONS &
CORRECT ANSWERS
Question 1.
A technique to get more performance from loops that access arrays, in which multiple copies of the
loop body are made and instructions from different iterations are scheduled together.
ANSWER
loop unrolling
Question 2.
The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to
memory or a register.
ANSWER
Reorder Buffer
Question 3.
An address that corresponds to a location in virtual space and is translated by address mapping to a
physical address when memory is accessed.
ANSWER
virtual address
Question 4.
A uniprocessor
ANSWER
Single Instruction Single Data (SISD)
,Question 5.
the 4-bit ALU control input using a small control unit that has as inputs the opcode field of the
instruction and a 2-bit control field
indicates whether the operation to be performed should be add (00) for loads and stores, pass input b
(01) for CBZ, or be determined by the operation encoded in the opcode field (10)
10 is ORR, AND, SUB, ADD (R-type)
00 is LDUR, STUR
01 is CBZ
ANSWER
ALUOp
Question 6.
data transfer instruction that copies data from memory to a register
ANSWER
load
Question 7.
The part of the computer architecture related to programming, including the native data types,
instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and
external I/O.
ANSWER
Instruction Set Architecture (ISA)
Question 8.
Programming language that has the same structure and set of commands as machine languages but
allows programmers to use symbolic representations of numeric machine code.
ANSWER
Assembly Language
,Question 9.
The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the
result of an operation to programmer-visible registers and memory.
ANSWER
commit unit
Question 10.
The fraction of memory accesses not found in a level of the memory hierarchy
ANSWER
Miss rate
Question 11.
An on/off switch controlled by an electric signal
ANSWER
Transistor
Question 12.
Nonvolatile memory used to store programs and data between runs; typically consists of flash
memory in PMDs and magnetic disks in servers.
ANSWER
Secondary memory
Question 13.
the amount of work performed by a system during a given period of time
ANSWER
throughput
, Question 14.
A branch predictor that combines local behavior of a particular branch and global information about
the behavior of some recent number of executed branches.
ANSWER
Correlating predictor
Question 15.
The unpopularity of imprecise interrupts led to the standard of commit units in dynamically scheduled
pipelined processors
ANSWER
Imprecise interupt
Question 16.
A technique that uses main memory as a "cache" for secondary storage
The address is broken into a virtual page number and a page offset
ANSWER
virtual memory
Question 17.
The principle stating that if a data location is referenced, data locations with nearby addresses will
tend to be referenced soon.
ANSWER
spatial locality
Question 18.
A structure that caches the destination PC or destination instruction for a branch. It is usually
organized as a cache with tags, making it more costly than a simple prediction buffer.
ANSWER
Branch target buffer
