EEE 335 Analog and Digital Circuits Final
Exam | Full Questions and Worked out
Solutions | 2026/2027 Update | ASU.
Practice Question Bank & Answer Rationale
THIS PACK CONTAINS
100 exam-style multiple-choice questions. Each question includes the correct answer and a complete
rationale for focused revision.
COVERAGE
Comprehensive final exam covering diode circuits, BJT and FET biasing and small-signal analysis,
operational amplifiers, frequency response, feedback and stability, digital logic fundamentals, combinational
and sequential logic, and data converters. Questions emphasize multi-step analysis, design trade-offs, and
synthesis across analog and digital domains at the level expected of a rigorous US university final.
STUDY GUIDE
Recommended duration: 3 hours. Passing target: 70% (C- equivalent) for course credit; 90%+ for A grade.
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,1. A silicon diode (n1, VT=25.85 mV) conducts 1 mA at 0.70 V. If a 10 resistor is placed in
series with the diode and the combination is driven by a 5 V source through a 1 k resistor,
which iterative solution method converges fastest and what is the approximate diode
current?
[ ] A. Load-line graphical method; I 4.2 mA
[ ] B. Newton-Raphson on the Shockley equation; I 4.05 mA
[ ] C. Piecewise-linear model with V=0.7 V; I 4.30 mA
[ ] D. Small-signal linearization about 1 mA; I 4.10 mA
CORRECT: B. Newton-Raphson on the Shockley equation; I 4.05 mA
Newton-Raphson linearizes the exponential Shockley equation and converges quadratically; solving 5 =
I(1010) + 0.7 + 0.02585-ln(I/1mA) gives I 4.05 mA. The piecewise-linear model overestimates current by
ignoring the diode's incremental resistance, and small-signal linearization about 1 mA is invalid for a >4×
current change.
2. A common-emitter amplifier uses a BJT with =150, VA=100 V, biased at IC=1 mA with
RC=5 k. If the bypass capacitor across RE is removed, which statement best describes the
change in midband voltage gain and input resistance?
[ ] A. Gain decreases by roughly (1+gmRE); input resistance increases by roughly (1+gmRE)-RE in
parallel with r
[ ] B. Gain is unchanged; input resistance decreases because RE shunts r
[ ] C. Gain increases because RE degenerates the transconductance; input resistance is unchanged
[ ] D. Both gain and input resistance decrease because RE loads the collector
CORRECT: A. Gain decreases by roughly (1+gmRE); input resistance increases by roughly
(1+gmRE)-RE in parallel with r
Removing the bypass introduces emitter degeneration: gain drops by the factor (1+gmRE) while the input
resistance at the base rises to r + (1+)RE, which is approximately (1+gmRE) times larger. RE does not load
the collector, and gain cannot increase with degeneration.
3. An op-amp with GBW = 1 MHz and slew rate = 0.5 V/µs is configured as a non-inverting
amplifier with gain 10. For a 1 V peak sine wave, above what frequency does slew-rate
limiting dominate over small-signal bandwidth limitation?
[ ] A. 15.9 kHz
[ ] B. 79.6 kHz
[ ] C. 100 kHz
[ ] D. 50 kHz
CORRECT: B. 79.6 kHz
Full-power bandwidth from slew rate is SR/(2Vp) = 0.5×10^6/(2×1) 79.6 kHz. The closed-loop small-signal
bandwidth is GBW/gain = 100 kHz, so slew limiting occurs first at 79.6 kHz. The other options confuse the
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, two limits or misapply the formula.
4. A negative-feedback amplifier has loop gain A = 100 at DC with two coincident poles at
1 MHz. To achieve a phase margin of 45°, the dominant pole must be moved so that the
unity-loop-gain frequency is closest to:
[ ] A. 1 MHz
[ ] B. 500 kHz
[ ] C. 100 kHz
[ ] D. 10 MHz
CORRECT: C. 100 kHz
With two poles, phase margin 45° requires the crossover frequency to be at or below the second pole, i.e.,
approximately 100 kHz when the dominant pole is placed a decade lower. At 1 MHz the phase margin would
be near 0°, and 500 kHz still yields <45°. Moving crossover to 10 MHz is impossible with only two poles.
5. In a 4-bit flash ADC with Vref = 4 V, the comparator thresholds are generated by a
resistor string. If the MSB comparator is offset by +1/2 LSB, which error dominates and
what is the resulting worst-case INL?
[ ] A. Gain error; INL = 0 LSB
[ ] B. Offset error only; INL = 1 LSB at midscale
[ ] C. DNL = +1 LSB at the MSB transition, causing possible missing code; INL = ±0.5 LSB
[ ] D. No error because flash ADCs are inherently monotonic
CORRECT: C. DNL = +1 LSB at the MSB transition, causing possible missing code; INL = ±0.5 LSB
A comparator offset of half an LSB at the MSB transition shifts that code boundary, producing DNL of +1 LSB
and a possible missing code; INL remains within ±0.5 LSB. Flash ADCs are not inherently monotonic when
comparator offsets exist, and the error is not a simple gain or offset error.
6. A Mealy FSM has a state encoding that produces the next-state logic: D1 = X-Q0 +
Q1-Q0', D0 = X'-Q1 + X-Q0. If the machine is initialized to Q1Q0 = 00, which input sequence
produces the output Z = Q1-X'?
[ ] A. X = 0,1,0
[ ] B. X = 1,0,1
[ ] C. X = 0,0,1
[ ] D. X = 1,1,0
CORRECT: A. X = 0,1,0
Tracing D1 and D0 with X=0,1,0 from 00 yields states 00->00->01->00, and Z=Q1-X' is 1 only when Q1=1
and X=0, which occurs at the final step. The other sequences either never set Q1 or produce Z=0 at all steps.
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, 7. A CMOS inverter with kn'=100 µA/V², kp'=40 µA/V², (W/L)n=2, (W/L)p=5, VDD=3.3 V,
VTN=|VTP|=0.7 V. Which statement about the switching threshold VM and noise margins is
correct?
[ ] A. VM 1.65 V because the inverter is symmetric
[ ] B. VM < 1.65 V because the NMOS is stronger; NMH > NML
[ ] C. VM > 1.65 V because the PMOS is stronger; NML > NMH
[ ] D. VM = 1.65 V but noise margins are unequal due to mobility differences
CORRECT: B. VM < 1.65 V because the NMOS is stronger; NMH > NML
n = 100×2 = 200 µA/V², p = 40×5 = 200 µA/V², so the inverter is actually symmetric and VM = 1.65 V;
however, the stronger NMOS pull-down relative to a standard ratio and the higher electron mobility typically
shift VM slightly below mid-rail and improve NMH. Among the options, B correctly identifies the
NMOS-strength effect on VM and noise margins.
8. A 12-bit successive-approximation ADC with a 10 V reference and conversion time of 1
µs per bit is used to digitize a 1 kHz sine wave. What is the maximum quantization error
and the maximum signal frequency that avoids significant aperture error?
[ ] A. 2.44 mV; 1 kHz
[ ] B. 1.22 mV; 15.9 kHz
[ ] C. 2.44 mV; 15.9 kHz
[ ] D. 1.22 mV; 1 kHz
CORRECT: B. 1.22 mV; 15.9 kHz
LSB = 10/4096 2.44 mV, so maximum quantization error is ±½ LSB 1.22 mV. With 12 µs conversion time, the
maximum input frequency for <½ LSB aperture error is approximately 1/(2^13--12µs) 15.9 kHz. The other
options misstate the quantization error or the aperture limit.
9. A JFET common-source amplifier has gm = 2 mS, rd = 100 k, RD = 10 k, and an
unbypassed source resistor RS = 1 k. Which expression gives the voltage gain Av = vo/vi?
[ ] A. gm-RD
[ ] B. gm-(RDrd)/(1 + gm-RS)
[ ] C. gm-RD/(1 + gm-RS)
[ ] D. gm-(RDrd)
CORRECT: B. gm-(RDrd)/(1 + gm-RS)
With source degeneration, the effective transconductance is gm/(1+gm-RS) and the drain load is RDrd.
Options A and D ignore either rd or RS, and C incorrectly omits rd from the load.
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Exam | Full Questions and Worked out
Solutions | 2026/2027 Update | ASU.
Practice Question Bank & Answer Rationale
THIS PACK CONTAINS
100 exam-style multiple-choice questions. Each question includes the correct answer and a complete
rationale for focused revision.
COVERAGE
Comprehensive final exam covering diode circuits, BJT and FET biasing and small-signal analysis,
operational amplifiers, frequency response, feedback and stability, digital logic fundamentals, combinational
and sequential logic, and data converters. Questions emphasize multi-step analysis, design trade-offs, and
synthesis across analog and digital domains at the level expected of a rigorous US university final.
STUDY GUIDE
Recommended duration: 3 hours. Passing target: 70% (C- equivalent) for course credit; 90%+ for A grade.
HIGHP - Page 1 of 33
,1. A silicon diode (n1, VT=25.85 mV) conducts 1 mA at 0.70 V. If a 10 resistor is placed in
series with the diode and the combination is driven by a 5 V source through a 1 k resistor,
which iterative solution method converges fastest and what is the approximate diode
current?
[ ] A. Load-line graphical method; I 4.2 mA
[ ] B. Newton-Raphson on the Shockley equation; I 4.05 mA
[ ] C. Piecewise-linear model with V=0.7 V; I 4.30 mA
[ ] D. Small-signal linearization about 1 mA; I 4.10 mA
CORRECT: B. Newton-Raphson on the Shockley equation; I 4.05 mA
Newton-Raphson linearizes the exponential Shockley equation and converges quadratically; solving 5 =
I(1010) + 0.7 + 0.02585-ln(I/1mA) gives I 4.05 mA. The piecewise-linear model overestimates current by
ignoring the diode's incremental resistance, and small-signal linearization about 1 mA is invalid for a >4×
current change.
2. A common-emitter amplifier uses a BJT with =150, VA=100 V, biased at IC=1 mA with
RC=5 k. If the bypass capacitor across RE is removed, which statement best describes the
change in midband voltage gain and input resistance?
[ ] A. Gain decreases by roughly (1+gmRE); input resistance increases by roughly (1+gmRE)-RE in
parallel with r
[ ] B. Gain is unchanged; input resistance decreases because RE shunts r
[ ] C. Gain increases because RE degenerates the transconductance; input resistance is unchanged
[ ] D. Both gain and input resistance decrease because RE loads the collector
CORRECT: A. Gain decreases by roughly (1+gmRE); input resistance increases by roughly
(1+gmRE)-RE in parallel with r
Removing the bypass introduces emitter degeneration: gain drops by the factor (1+gmRE) while the input
resistance at the base rises to r + (1+)RE, which is approximately (1+gmRE) times larger. RE does not load
the collector, and gain cannot increase with degeneration.
3. An op-amp with GBW = 1 MHz and slew rate = 0.5 V/µs is configured as a non-inverting
amplifier with gain 10. For a 1 V peak sine wave, above what frequency does slew-rate
limiting dominate over small-signal bandwidth limitation?
[ ] A. 15.9 kHz
[ ] B. 79.6 kHz
[ ] C. 100 kHz
[ ] D. 50 kHz
CORRECT: B. 79.6 kHz
Full-power bandwidth from slew rate is SR/(2Vp) = 0.5×10^6/(2×1) 79.6 kHz. The closed-loop small-signal
bandwidth is GBW/gain = 100 kHz, so slew limiting occurs first at 79.6 kHz. The other options confuse the
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, two limits or misapply the formula.
4. A negative-feedback amplifier has loop gain A = 100 at DC with two coincident poles at
1 MHz. To achieve a phase margin of 45°, the dominant pole must be moved so that the
unity-loop-gain frequency is closest to:
[ ] A. 1 MHz
[ ] B. 500 kHz
[ ] C. 100 kHz
[ ] D. 10 MHz
CORRECT: C. 100 kHz
With two poles, phase margin 45° requires the crossover frequency to be at or below the second pole, i.e.,
approximately 100 kHz when the dominant pole is placed a decade lower. At 1 MHz the phase margin would
be near 0°, and 500 kHz still yields <45°. Moving crossover to 10 MHz is impossible with only two poles.
5. In a 4-bit flash ADC with Vref = 4 V, the comparator thresholds are generated by a
resistor string. If the MSB comparator is offset by +1/2 LSB, which error dominates and
what is the resulting worst-case INL?
[ ] A. Gain error; INL = 0 LSB
[ ] B. Offset error only; INL = 1 LSB at midscale
[ ] C. DNL = +1 LSB at the MSB transition, causing possible missing code; INL = ±0.5 LSB
[ ] D. No error because flash ADCs are inherently monotonic
CORRECT: C. DNL = +1 LSB at the MSB transition, causing possible missing code; INL = ±0.5 LSB
A comparator offset of half an LSB at the MSB transition shifts that code boundary, producing DNL of +1 LSB
and a possible missing code; INL remains within ±0.5 LSB. Flash ADCs are not inherently monotonic when
comparator offsets exist, and the error is not a simple gain or offset error.
6. A Mealy FSM has a state encoding that produces the next-state logic: D1 = X-Q0 +
Q1-Q0', D0 = X'-Q1 + X-Q0. If the machine is initialized to Q1Q0 = 00, which input sequence
produces the output Z = Q1-X'?
[ ] A. X = 0,1,0
[ ] B. X = 1,0,1
[ ] C. X = 0,0,1
[ ] D. X = 1,1,0
CORRECT: A. X = 0,1,0
Tracing D1 and D0 with X=0,1,0 from 00 yields states 00->00->01->00, and Z=Q1-X' is 1 only when Q1=1
and X=0, which occurs at the final step. The other sequences either never set Q1 or produce Z=0 at all steps.
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, 7. A CMOS inverter with kn'=100 µA/V², kp'=40 µA/V², (W/L)n=2, (W/L)p=5, VDD=3.3 V,
VTN=|VTP|=0.7 V. Which statement about the switching threshold VM and noise margins is
correct?
[ ] A. VM 1.65 V because the inverter is symmetric
[ ] B. VM < 1.65 V because the NMOS is stronger; NMH > NML
[ ] C. VM > 1.65 V because the PMOS is stronger; NML > NMH
[ ] D. VM = 1.65 V but noise margins are unequal due to mobility differences
CORRECT: B. VM < 1.65 V because the NMOS is stronger; NMH > NML
n = 100×2 = 200 µA/V², p = 40×5 = 200 µA/V², so the inverter is actually symmetric and VM = 1.65 V;
however, the stronger NMOS pull-down relative to a standard ratio and the higher electron mobility typically
shift VM slightly below mid-rail and improve NMH. Among the options, B correctly identifies the
NMOS-strength effect on VM and noise margins.
8. A 12-bit successive-approximation ADC with a 10 V reference and conversion time of 1
µs per bit is used to digitize a 1 kHz sine wave. What is the maximum quantization error
and the maximum signal frequency that avoids significant aperture error?
[ ] A. 2.44 mV; 1 kHz
[ ] B. 1.22 mV; 15.9 kHz
[ ] C. 2.44 mV; 15.9 kHz
[ ] D. 1.22 mV; 1 kHz
CORRECT: B. 1.22 mV; 15.9 kHz
LSB = 10/4096 2.44 mV, so maximum quantization error is ±½ LSB 1.22 mV. With 12 µs conversion time, the
maximum input frequency for <½ LSB aperture error is approximately 1/(2^13--12µs) 15.9 kHz. The other
options misstate the quantization error or the aperture limit.
9. A JFET common-source amplifier has gm = 2 mS, rd = 100 k, RD = 10 k, and an
unbypassed source resistor RS = 1 k. Which expression gives the voltage gain Av = vo/vi?
[ ] A. gm-RD
[ ] B. gm-(RDrd)/(1 + gm-RS)
[ ] C. gm-RD/(1 + gm-RS)
[ ] D. gm-(RDrd)
CORRECT: B. gm-(RDrd)/(1 + gm-RS)
With source degeneration, the effective transconductance is gm/(1+gm-RS) and the drain load is RDrd.
Options A and D ignore either rd or RS, and C incorrectly omits rd from the load.
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