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EEE 120 Quiz 6 Requires Respondus LockDown Browser + Webcam Q&A | Graded A+ | Fall Update

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EEE 120 Quiz 6 Requires Respondus LockDown Browser + Webcam Q&A | Graded A+ | Fall Update

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EEE 120 Quiz 6 Requires Respondus LockDown Browser +
Webcam Q&A | Graded A+ | Fall Update 2026-2027


1. Which of the following best describes the primary function of a flip-flop in a digital
system?
A) To perform binary addition of two numbers
B) To store one bit of data and change state only on a clock edge
C) To select one of several inputs and route it to a single output
D) To convert analog signals to digital signals
Correct Answer: To store one bit of data and change state only on a clock edge
Rationale: A flip-flop is an edge-triggered memory element that stores a single bit. Its output
changes only on the active clock edge (rising or falling), making it essential for synchronous
sequential circuits. It does not perform arithmetic, route data like a multiplexer, or convert
analog signals.
2. What is the primary characteristic of a latch compared to a flip-flop?
A) A latch is edge-triggered, while a flip-flop is level-sensitive
B) A latch is level-sensitive and transparent when the enable signal is active
C) A latch stores multiple bits, while a flip-flop stores one bit
D) A latch requires a clock signal, while a flip-flop does not
Correct Answer: A latch is level-sensitive and transparent when the enable signal is active
Rationale: A latch is level-sensitive, meaning its output follows the input when the enable signal
is at the active level (transparent). A flip-flop is edge-triggered and only changes state on a clock
edge. Latches typically store one bit and do not require a clock.
3. According to the EEE 120 Quiz 6 blueprint, which topic area carries the highest
percentage of exam questions?
A) Number systems and binary arithmetic
B) Boolean algebra and logic minimization
C) Sequential logic design, flip-flops, and state machines
D) Combinational logic and Karnaugh maps
Correct Answer: Sequential logic design, flip-flops, and state machines
Rationale: The EEE 120 Quiz 6 blueprint explicitly focuses on sequential logic design, including
flip-flops, registers, counters, timing diagrams, and state machines (Moore and Mealy). While

,number systems and Boolean algebra are foundational, the primary emphasis of Quiz 6 is on
sequential circuits.
4. What is the minimum number of flip-flops required to implement a state machine with
37 states?
A) 5
B) 6
C) 7
D) 8
Correct Answer: 6
Rationale: The number of flip-flops needed is the smallest integer n such that 2^n ≥ number of
states. For 37 states, 2^5 = 32 (too few) and 2^6 = 64 (enough), so 6 flip-flops are required. This
is a standard calculation in state machine design.
5. Which of the following is a characteristic of a Moore state machine?
A) The output depends on both the current state and the current inputs
B) The output depends only on the current state
C) The output changes immediately when inputs change
D) The output is independent of the state
Correct Answer: The output depends only on the current state
Rationale: In a Moore machine, the output is determined solely by the current state. This makes
the output stable for the entire clock cycle and synchronized with state transitions. Mealy
machine outputs depend on both state and inputs.
6. What is the primary advantage of a Mealy machine over a Moore machine?
A) Outputs are more stable and synchronized with the clock
B) It often requires fewer states to implement the same functionality
C) It is easier to design and debug
D) It always runs at a higher clock frequency
Correct Answer: It often requires fewer states to implement the same functionality
Rationale: Because Mealy outputs depend on inputs as well as state, a Mealy machine can
sometimes implement a given function with fewer states than an equivalent Moore machine.
Moore machines have more stable outputs that are synchronized with the clock.
7. Which of the following best describes the setup time of a flip-flop?
A) The time the data input must be stable before the active clock edge
B) The time the data input must be stable after the active clock edge

, C) The time it takes for the output to change after the clock edge
D) The time between two consecutive clock edges
Correct Answer: The time the data input must be stable before the active clock edge
Rationale: Setup time is the minimum amount of time before the active clock edge that the
data input must be stable for the flip-flop to reliably capture the data. Hold time is the time
after the clock edge, and propagation delay is the output delay.
8. What is the primary function of a shift register?
A) To count clock pulses and produce a binary output
B) To shift data bits from one stage to the next in a serial or parallel manner
C) To perform arithmetic addition of two binary numbers
D) To generate clock signals for a sequential circuit
Correct Answer: To shift data bits from one stage to the next in a serial or parallel manner
Rationale: A shift register is a cascade of flip-flops that can shift data bits from one stage to the
next. It is commonly used for serial-to-parallel and parallel-to-serial data conversion. It does not
count pulses, perform arithmetic, or generate clocks.
9. Which type of shift register allows data to be loaded in parallel and shifted out serially?
A) Serial-in, serial-out (SISO)
B) Parallel-in, serial-out (PISO)
C) Serial-in, parallel-out (SIPO)
D) Parallel-in, parallel-out (PIPO)
Correct Answer: Parallel-in, serial-out (PISO)
Rationale: A PISO shift register accepts data in parallel and outputs it serially, one bit at a time.
SISO shifts data in and out serially, SIPO accepts serial input and outputs in parallel, and PIPO
accepts and outputs data in parallel.
10. How many states does a 4-bit binary counter have?
A) 4
B) 8
C) 16
D) 32
Correct Answer: 16
Rationale: An n-bit binary counter has 2^n states, counting from 0 to 2^n - 1. For 4 bits, 2^4 =
16 states (0 to 15). A 3-bit counter has 8 states, and a 5-bit counter has 32 states.

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