EEE 334 CIRCUITS II - QUIZ 7: DIGITAL CMOS |
QUESTIONS WITH CORRECT ANSWERS |
100% SCORE | 2026 UPDATE - ASU.
149 Questions with Answers and Detailed Rationales
100 PERCENT GUARANTEED PASS
INSTANT DOWNLOAD ANSWERS INCLUDED
IMPORTANCE OF THIS DOCUMENT
This comprehensive examination preparation guide has been meticulously developed to help you succeed in the
EEE 334 CIRCUITS II - QUIZ 7: DIGITAL CMOS | QUESTIONS WITH CORRECT ANSWERS | 100% SCORE |
2026 UPDATE - ASU.. It contains 149 carefully selected questions that reflect the most current exam content and
testing strategies. Each question is accompanied by a correct answer and a detailed rationale that explains the
underlying pathophysiology, pharmacology, or clinical reasoning.
Self-Assessment – Test your knowledge and Exam Preparation – Familiarize yourself with the
identify areas requiring further question format and content
study areas
Concept Reinforcement – Deepen your Confidence Building – Develop test-taking
understanding through strategies and reduce
evidence-based exam anxiety
rationales
Time Management – Practice answering
questions under simulated
exam conditions
Review Summary 149 Questions
Foundations - Application - EEE 334 Circuits II 7 Digital CMOS WITH Correct 100 Score 2026 Update -
ASU Digital CMOS Circuit Design AND Analysis Undergraduate YEAR 3 Electrical Engineering ASU EEE 334
Circuits II
All answers with rationales
,Table of Contents
Content Area Questions Key Topics
MOS Transistor Theory AND 1-25 Inverter, Logic, Transistor, Threshold, Dynamic
Operation
CMOS Logic Gates AND 26-50 Inverter, Dynamic, Logic GATE, Transistor, LOAD Capacitance
Static Characteristics
Dynamic Characteristics AND 51-75 Inverter, Static CMOS, Output, Dynamic, Transistor
Power Dissipation
Combinational Logic Design 76-100 Inverter, Logic, Delay, Propagation, Transistor
IN CMOS
Sequential Logic Circuits 101-125 Inverter, Logic, Dynamic, Transistor, Propagation Delay
AND Timing
CMOS Fabrication AND 126-149 Inverter, Logic, Dynamic, Power, Switching Threshold
Layout
TOTAL 149 All questions include answers and detailed rationales
,Section A - MOS Transistor Theory AND Operation
Q1.
A symmetric CMOS inverter is designed with (W/L)n = 2 and (W/L)p = 4 in a 0.18 µm
process where µnCox = 4µpCox. Which statement best describes the switching threshold
VM relative to VDD/2?
A. VM = VDD/2 because the B. VM > VDD/2 because the NMOS is
transconductance parameters are equal stronger
C. VM < VDD/2 because the PMOS is D. VM = VDD/2 only if Vtn = |Vtp| exactly
weaker and n = p
Correct: D - VM = VDD/2 only if Vtn = |Vtp| exactly and n = p
Rationale:Switching threshold VM = VDD/2 requires ²n = ²p AND Vtn = |Vtp|; here ²n =
2-4µpCox and p = 4-µpCox, so n = 2p, making VM slightly below VDD/2 unless threshold
voltages are also matched. The symmetric-inverter condition is a joint constraint on both ratio
and threshold voltages, not just one.
Why the other answers are wrong:
A. Transconductance parameters are not equal here (n = 2p), so VM VDD/2 by default.
B. A stronger NMOS pulls VM below VDD/2, not above.
C. The PMOS is not weaker-its is half the NMOS , but the correct condition also involves
threshold matching.
Reference: Rabaey, Chandrakasan & Nikolic, Digital Integrated Circuits, 2nd Ed., Ch. 5 (CMOS Inverter
VTC).
Q2.
For a static CMOS 3-input NOR gate driving an identical NOR gate, which input
combination yields the WORST-case (largest) pull-down resistance path?
A. All three inputs high (A=B=C=1) B. Only one input high
C. All three inputs low D. Two inputs high, one low
Correct: B - Only one input high
Rationale:In a NOR gate, NMOS devices are in parallel; only one NMOS is on when a single
input is high, so the pull-down is a single transistor resistance. With multiple inputs high,
multiple parallel NMOS devices reduce the effective resistance, so the worst-case (largest)
resistance occurs with only one input high.
Why the other answers are wrong:
A. All three high turns on three parallel NMOS devices, giving the LOWEST pull-down
resistance.
Page 3
, Section A - MOS Transistor Theory AND Operation
C. All low means NMOS stack is off-no pull-down path exists, so this is not a valid worst-case
path.
D. Two high gives two parallel NMOS devices, lower resistance than a single device.
Reference: Weste & Harris, CMOS VLSI Design, 4th Ed., Ch. 2 (CMOS Logic Gate Design).
Q3.
A dynamic logic gate precharges node X to VDD and evaluates through an NMOS logic
block. If the input to a transistor in the logic block is high during precharge, what failure
mode can occur?
A. Charge sharing through the input B. Clock feedthrough from the precharge
transistor transistor
C. Body-effect-induced threshold shift D. Subthreshold leakage from the output
inverter
Correct: A - Charge sharing through the input transistor
Rationale:If an input transistor is on during precharge, the internal node capacitance in the
logic block can share charge with the precharged output node, reducing the precharged
voltage and corrupting the evaluated logic level. This is classic charge sharing, mitigated by
precharging internal nodes or adding keepers.
Why the other answers are wrong:
B. Clock feedthrough concerns capacitive coupling of the clock to the output, not input
transistors being on during precharge.
C. Body effect shifts threshold but is not the failure mode tied to inputs being high during
precharge.
D. Subthreshold leakage is a separate concern (charge leakage) and does not require inputs to
be high during precharge.
Reference: Rabaey et al., Digital Integrated Circuits, 2nd Ed., Ch. 6 (Dynamic Logic).
Q4.
A CMOS inverter drives a load capacitance CL = 50 fF. If the average supply current during
a full charge/discharge cycle is 20 µA at VDD = 1.8 V and f = 100 MHz, what is the dynamic
power dissipation?
A. 3.6 µW B. 16.2 µW
C. 32.4 µW D. 64.8 µW
Correct: B - 16.2 µW
Rationale:Dynamic power P = CL·VDD²·f = 50e-15 × (1.8)² × 100e6 = 50e-15 × 3.24 × 1e8 =
16.2 µW. The average-current value is a distractor; the standard formula uses CL, VDD, and
f.
Page 4
QUESTIONS WITH CORRECT ANSWERS |
100% SCORE | 2026 UPDATE - ASU.
149 Questions with Answers and Detailed Rationales
100 PERCENT GUARANTEED PASS
INSTANT DOWNLOAD ANSWERS INCLUDED
IMPORTANCE OF THIS DOCUMENT
This comprehensive examination preparation guide has been meticulously developed to help you succeed in the
EEE 334 CIRCUITS II - QUIZ 7: DIGITAL CMOS | QUESTIONS WITH CORRECT ANSWERS | 100% SCORE |
2026 UPDATE - ASU.. It contains 149 carefully selected questions that reflect the most current exam content and
testing strategies. Each question is accompanied by a correct answer and a detailed rationale that explains the
underlying pathophysiology, pharmacology, or clinical reasoning.
Self-Assessment – Test your knowledge and Exam Preparation – Familiarize yourself with the
identify areas requiring further question format and content
study areas
Concept Reinforcement – Deepen your Confidence Building – Develop test-taking
understanding through strategies and reduce
evidence-based exam anxiety
rationales
Time Management – Practice answering
questions under simulated
exam conditions
Review Summary 149 Questions
Foundations - Application - EEE 334 Circuits II 7 Digital CMOS WITH Correct 100 Score 2026 Update -
ASU Digital CMOS Circuit Design AND Analysis Undergraduate YEAR 3 Electrical Engineering ASU EEE 334
Circuits II
All answers with rationales
,Table of Contents
Content Area Questions Key Topics
MOS Transistor Theory AND 1-25 Inverter, Logic, Transistor, Threshold, Dynamic
Operation
CMOS Logic Gates AND 26-50 Inverter, Dynamic, Logic GATE, Transistor, LOAD Capacitance
Static Characteristics
Dynamic Characteristics AND 51-75 Inverter, Static CMOS, Output, Dynamic, Transistor
Power Dissipation
Combinational Logic Design 76-100 Inverter, Logic, Delay, Propagation, Transistor
IN CMOS
Sequential Logic Circuits 101-125 Inverter, Logic, Dynamic, Transistor, Propagation Delay
AND Timing
CMOS Fabrication AND 126-149 Inverter, Logic, Dynamic, Power, Switching Threshold
Layout
TOTAL 149 All questions include answers and detailed rationales
,Section A - MOS Transistor Theory AND Operation
Q1.
A symmetric CMOS inverter is designed with (W/L)n = 2 and (W/L)p = 4 in a 0.18 µm
process where µnCox = 4µpCox. Which statement best describes the switching threshold
VM relative to VDD/2?
A. VM = VDD/2 because the B. VM > VDD/2 because the NMOS is
transconductance parameters are equal stronger
C. VM < VDD/2 because the PMOS is D. VM = VDD/2 only if Vtn = |Vtp| exactly
weaker and n = p
Correct: D - VM = VDD/2 only if Vtn = |Vtp| exactly and n = p
Rationale:Switching threshold VM = VDD/2 requires ²n = ²p AND Vtn = |Vtp|; here ²n =
2-4µpCox and p = 4-µpCox, so n = 2p, making VM slightly below VDD/2 unless threshold
voltages are also matched. The symmetric-inverter condition is a joint constraint on both ratio
and threshold voltages, not just one.
Why the other answers are wrong:
A. Transconductance parameters are not equal here (n = 2p), so VM VDD/2 by default.
B. A stronger NMOS pulls VM below VDD/2, not above.
C. The PMOS is not weaker-its is half the NMOS , but the correct condition also involves
threshold matching.
Reference: Rabaey, Chandrakasan & Nikolic, Digital Integrated Circuits, 2nd Ed., Ch. 5 (CMOS Inverter
VTC).
Q2.
For a static CMOS 3-input NOR gate driving an identical NOR gate, which input
combination yields the WORST-case (largest) pull-down resistance path?
A. All three inputs high (A=B=C=1) B. Only one input high
C. All three inputs low D. Two inputs high, one low
Correct: B - Only one input high
Rationale:In a NOR gate, NMOS devices are in parallel; only one NMOS is on when a single
input is high, so the pull-down is a single transistor resistance. With multiple inputs high,
multiple parallel NMOS devices reduce the effective resistance, so the worst-case (largest)
resistance occurs with only one input high.
Why the other answers are wrong:
A. All three high turns on three parallel NMOS devices, giving the LOWEST pull-down
resistance.
Page 3
, Section A - MOS Transistor Theory AND Operation
C. All low means NMOS stack is off-no pull-down path exists, so this is not a valid worst-case
path.
D. Two high gives two parallel NMOS devices, lower resistance than a single device.
Reference: Weste & Harris, CMOS VLSI Design, 4th Ed., Ch. 2 (CMOS Logic Gate Design).
Q3.
A dynamic logic gate precharges node X to VDD and evaluates through an NMOS logic
block. If the input to a transistor in the logic block is high during precharge, what failure
mode can occur?
A. Charge sharing through the input B. Clock feedthrough from the precharge
transistor transistor
C. Body-effect-induced threshold shift D. Subthreshold leakage from the output
inverter
Correct: A - Charge sharing through the input transistor
Rationale:If an input transistor is on during precharge, the internal node capacitance in the
logic block can share charge with the precharged output node, reducing the precharged
voltage and corrupting the evaluated logic level. This is classic charge sharing, mitigated by
precharging internal nodes or adding keepers.
Why the other answers are wrong:
B. Clock feedthrough concerns capacitive coupling of the clock to the output, not input
transistors being on during precharge.
C. Body effect shifts threshold but is not the failure mode tied to inputs being high during
precharge.
D. Subthreshold leakage is a separate concern (charge leakage) and does not require inputs to
be high during precharge.
Reference: Rabaey et al., Digital Integrated Circuits, 2nd Ed., Ch. 6 (Dynamic Logic).
Q4.
A CMOS inverter drives a load capacitance CL = 50 fF. If the average supply current during
a full charge/discharge cycle is 20 µA at VDD = 1.8 V and f = 100 MHz, what is the dynamic
power dissipation?
A. 3.6 µW B. 16.2 µW
C. 32.4 µW D. 64.8 µW
Correct: B - 16.2 µW
Rationale:Dynamic power P = CL·VDD²·f = 50e-15 × (1.8)² × 100e6 = 50e-15 × 3.24 × 1e8 =
16.2 µW. The average-current value is a distractor; the standard formula uses CL, VDD, and
f.
Page 4
