ITE 221 EXAM 2 UPDATED ACTUAL QUESTIONS AND CORRECT ANSWERS

ITE 221 EXAM 2 UPDATED ACTUAL QUESTIONS AND
CORRECT ANSWERS

Question:
1. Address bus
Answer:
The portion of the system bus that transmits a memory address when the primary storage is the sending or
receiving device

Question:
2. buffer
Answer:
A small reserved area of main memory (usually DRAM or SDRAM) that holds data in transit from one
device to another and it is used to resolve differences in data transfer unit size

Question:
3. Buffer overflow
Answer:
An error condition that results when receiving more data than can be stored in a buffer

Question:
4. bus
Answer:
A shared electrical or optical communication channel that connects two or more devices in a computer
network

Question:
5. bus arbitration unit
Answer:
a simpler processor attached to a peer to peer bus that decides which devices want to become a bus master

Question:
6. bus clock
Answer:
A clock circuit that generates timing pulses, which are transmitted to all devices attached to the system bus
to coordinate their activities

Question:
7. bus cycle
Answer:
The time interval from one bus clock pulse to the next; also the time required to perform one data transfer
operation on a bus

Question:
8. bus master

,Answer:
A device attached to a bus that can intimate a data transfer operation or send a command to another device;
it controls all access to the bus

Question:
9. bus protocol
Answer:
a communication protocol, used by all devices attached to a bus, that governs the format, content and
timing of data memory address and control message sent across the bus

Question:
10. bus slave
Answer:
Devices that must go through the bus master for access to the bus

Question:
11. cache
Answer:
An area of high-speed memory (usually RAM) for storage device accesses that improves the performance
of read and write operation

Question:
12. cache controller
Answer:
A special-purposes processor or software that manages cache content, it guesses what data will be
requested un the near future and loads this data from the storage device into the cache before it's actually
requested.

Question:
13. cache hit
Answer:
An access to data already contained in the cache

Question:
14. cache miss
Answer:
An access to data that isn't stored in the cache

Question:
15. cache swap
Answer:
An operation performed after a cache miss. The cache controller guesses which data is least likely to be
needed in the near future, writes it to the storage device, and purges it from the cache. The requested data is
then read from the storage devices and placed in the cache

Question:
16. compression

, Answer:
A technique that reduces the number of bits used to encode data

Question:
17. compression algorithm
Answer:
a mathematical compression technique implemented as a program for translating data inputs into
equivalent but smaller data outputs

Question:
18. control bus
Answer:
the portion of the system bus that carries commands, command responses, status codes, and similar
messages; computer components coordinate theri activities by sending signals over this bus

Question:
19. core
Answer:
a term describing the logic, computation, and control circuitry of a single CPU

Question:
20. data bus
Answer:
the portion of the system bus that transmits data between computer components

Question:
21. decompression algorithm
Answer:
an algorithm that restores compressed stat to its origanl or nearly original state

Question:
22. device controller
Answer:
a processor that controls the physical actions of storage and I/O devices; connects these devices to the
system bus or a subsidiary

Question:
23. direct memory access
Answer:
A method of data transfer that enables the CPU to execute instructions while another device (DAM
controller) manages all transfers between memory and other storage or I/O devices

Question:
24. DMA controller
Answer:
A device attached to the system bus and main memory that manages data transfers, freeing the CPU to
execute instruction