CDA 3100 MIDTERM EXAMS ANSWERS AND
QUESTIONS SET A+
The Exclusive Or gate is unique and very important in Computer Science. The Truth
Table of the Exclusive Or gate is such that given an input A and B, the XOR gate
produces a 1 if and only if: - ✔✔Either A or B is one but not both
✔✔2-4 Decoder - ✔✔
✔✔2 Input Multiplexer - ✔✔
✔✔Program Logic Array - ✔✔
✔✔Identity Law - ✔✔addition:
a+0=a
multipication:
ax1=a
✔✔zero and one laws - ✔✔A*0 = 0
A+1 = 1
✔✔Inverse Law - ✔✔A+A' = A
A*A' = 0
✔✔Idempotent Laws - ✔✔A+A = A
A*A = A
✔✔Double Negation Law - ✔✔A'' = A
✔✔Absorption Laws - ✔✔A*(A+B) = A
A +( A*B ) = A
✔✔Commutative Laws - ✔✔A+B = B+A
, ✔✔Associative Laws - ✔✔A+(B+C) = (A+B) + C
✔✔Distributive Laws - ✔✔A*(B+C) = A*B + A*C
✔✔DeMorgan's Law - ✔✔(A+B)' = A' * B'
(A*B)' = A' + B'
✔✔Which one of the following equations is in Sum-Of-Products form? - ✔✔(A*B) +
(A'*B')
✔✔Modern day computers are built entirely using either NAND or NO gates. Which one
of the Great Architecture Principles does this illustrate? - ✔✔Make the simple case fast
✔✔Clock - ✔✔A signal that oscillates between low and high voltages in a fixed period of
time
✔✔Clock Cycle Time or Clock Period - ✔✔the time between two transitions from a low
volt to a high volt ( rising edges ) or the time between a high volt to a low volt ( falling
edges )
✔✔edge-triggered clocking - ✔✔A clocking scheme in which all state changes occur on
a active (rising or falling) clock edge.
✔✔State Element - ✔✔Has some type of Internal Storage and at least two inputs and
one output
✔✔Required Inputs to a State Element - ✔✔Data value to be written and the clock
signal, which indicates when the data value is to be written.
✔✔Output from a State Element - ✔✔The value that was written on a previous cycle.
✔✔Synchronous System - ✔✔logic system that employs clocks and data signals are
read only when the clock indicates that the signal values are stable (non changing)
✔✔Latches and Flip-flops - ✔✔The simplest state elements
✔✔Difference between Latch and Flip-FLop - ✔✔Clocked Latch state changes when
the clock signal is asserted. In a flip-flop the state is changed ONLY on an active (rising
or falling) clock edge.
✔✔What is a MIPS exception? - ✔✔An unexpected event originating from within the
processor.
- Invocation of the operating system
QUESTIONS SET A+
The Exclusive Or gate is unique and very important in Computer Science. The Truth
Table of the Exclusive Or gate is such that given an input A and B, the XOR gate
produces a 1 if and only if: - ✔✔Either A or B is one but not both
✔✔2-4 Decoder - ✔✔
✔✔2 Input Multiplexer - ✔✔
✔✔Program Logic Array - ✔✔
✔✔Identity Law - ✔✔addition:
a+0=a
multipication:
ax1=a
✔✔zero and one laws - ✔✔A*0 = 0
A+1 = 1
✔✔Inverse Law - ✔✔A+A' = A
A*A' = 0
✔✔Idempotent Laws - ✔✔A+A = A
A*A = A
✔✔Double Negation Law - ✔✔A'' = A
✔✔Absorption Laws - ✔✔A*(A+B) = A
A +( A*B ) = A
✔✔Commutative Laws - ✔✔A+B = B+A
, ✔✔Associative Laws - ✔✔A+(B+C) = (A+B) + C
✔✔Distributive Laws - ✔✔A*(B+C) = A*B + A*C
✔✔DeMorgan's Law - ✔✔(A+B)' = A' * B'
(A*B)' = A' + B'
✔✔Which one of the following equations is in Sum-Of-Products form? - ✔✔(A*B) +
(A'*B')
✔✔Modern day computers are built entirely using either NAND or NO gates. Which one
of the Great Architecture Principles does this illustrate? - ✔✔Make the simple case fast
✔✔Clock - ✔✔A signal that oscillates between low and high voltages in a fixed period of
time
✔✔Clock Cycle Time or Clock Period - ✔✔the time between two transitions from a low
volt to a high volt ( rising edges ) or the time between a high volt to a low volt ( falling
edges )
✔✔edge-triggered clocking - ✔✔A clocking scheme in which all state changes occur on
a active (rising or falling) clock edge.
✔✔State Element - ✔✔Has some type of Internal Storage and at least two inputs and
one output
✔✔Required Inputs to a State Element - ✔✔Data value to be written and the clock
signal, which indicates when the data value is to be written.
✔✔Output from a State Element - ✔✔The value that was written on a previous cycle.
✔✔Synchronous System - ✔✔logic system that employs clocks and data signals are
read only when the clock indicates that the signal values are stable (non changing)
✔✔Latches and Flip-flops - ✔✔The simplest state elements
✔✔Difference between Latch and Flip-FLop - ✔✔Clocked Latch state changes when
the clock signal is asserted. In a flip-flop the state is changed ONLY on an active (rising
or falling) clock edge.
✔✔What is a MIPS exception? - ✔✔An unexpected event originating from within the
processor.
- Invocation of the operating system
