AIR FORCE ELECTRONIC DATA PROCESSING TEST (EDPT) EXAM
PRACTICE QUESTIONS AND CORRECT ANSWERS (VERIFIED
ANSWERS) PLUS RATIONALES Q&A INSTANT DOWNLOAD PDF
140 QUESTIONS
TABLE OF CONTENTS
# TOPIC
1 Analyze and evaluate computer architecture and data representation
2 Apply advanced algorithms and data structures to solve computational problems
3 Assess operating system and network security principles
4 Synthesize database design and query optimization techniques
5 Critically evaluate system interoperability and emerging technologies
6 Air Force Electronic Data Processing Test
7 EDPT
8 Exam Practice Questions And Correct Answers
9 Verified Answers
10 Plus Rationales Q&A Instant Download Pdf
11 Foundations of Air Force Electronic Data Processing Test (EDPT)
12 Applied Air Force Electronic Data Processing Test (EDPT)
13 Advanced Air Force Electronic Data Processing Test (EDPT)
14 Air Force Electronic Data Processing Test (EDPT) Review
Page 1
,Q1 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In a real-time embedded system for avionics, a data race occurs between a
high-priority interrupt handler and a low-priority background task sharing a 32-bit
status register. Which synchronization primitive is most appropriate to ensure
atomicity without causing priority inversion or unbounded blocking?
A. Spinlock with disable interrupts
B. Mutex with priority inheritance
C. Non-blocking read-modify-write using atomic hardware instructions CORRECT
D. Semaphore with FIFO waiting queue
RATIONALE: Non-blocking atomic operations (e.g., CAS) avoid blocking and priority inversion,
ideal for short critical sections in real-time systems. Spinlocks can waste CPU and cause
inversion; mutexes and semaphores may block and cause inversion unless enhanced.
Q2 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
Given a relational schema R(A,B,C,D) with functional dependencies A->B, B->C,
and C->D, what is the highest normal form that R satisfies?
A. 1NF
B. 2NF CORRECT
C. 3NF
D. BCNF
RATIONALE: R has a transitive dependency A->B->C->D, so it violates 3NF. It is in 2NF because
the key is A (single attribute), and no partial dependency exists. BCNF requires every
determinant to be a candidate key, which is not the case.
Page 2
,Q3 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In TCP/IP networking, which mechanism allows a router to fragment an IPv6
packet?
A. The router uses the Fragment Offset field in the IPv6 header.
B. The router uses the Fragment Extension Header.
C. The router uses the Identification field and flags in the base header.
D. IPv6 routers do not fragment packets; fragmentation is done only by the source host.
CORRECT
RATIONALE: IPv6 routers do not perform fragmentation; only the source host can fragment using
extension headers. This simplifies router processing and relies on path MTU discovery. Options
A and C describe IPv4 mechanisms.
Q4 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
A cryptographic hash function H is used to ensure file integrity. An attacker finds
two distinct messages m1 and m2 such that H(m1) = H(m2). Which security
property is violated?
A. Preimage resistance
B. Second preimage resistance
C. Collision resistance CORRECT
D. Avalanche effect
RATIONALE: Finding any two distinct messages with the same hash violates collision resistance.
Second preimage resistance is about finding a different message with the same hash as a given
message; preimage resistance is about finding any message for a given hash. Avalanche effect
is not a security property but a diffusion property.
Page 3
, Q5 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In a distributed database system, a transaction needs to be executed across
multiple nodes. Which isolation level ensures that the transaction sees a
consistent snapshot of the database as of the start of the transaction, even if other
transactions commit concurrently?
A. Read Committed
B. Repeatable Read
C. Serializable
D. Snapshot Isolation CORRECT
RATIONALE: Snapshot isolation provides each transaction with a consistent snapshot at start,
avoiding dirty reads and non-repeatable reads, but not all anomalies (e.g., write skew).
Serializable ensures full serializability but may block more. Read Committed allows
non-repeatable reads.
Q6 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
Which of the following best describes the fundamental difference between RISC
and CISC instruction set architectures?
A. RISC has a larger number of instructions than CISC.
B. RISC instructions are generally executed in a single clock cycle, while CISC instructions may
take multiple cycles. CORRECT
C. CISC uses a load-store architecture, while RISC allows memory operands in arithmetic
instructions.
D. RISC uses microcode to implement complex instructions, while CISC uses hardwired control.
RATIONALE: RISC emphasizes simple, fixed-length instructions that can execute in one cycle,
with load-store architecture. CISC has complex instructions that may take multiple cycles and
often use microcode. Option C reverses the load-store property.
Page 4
PRACTICE QUESTIONS AND CORRECT ANSWERS (VERIFIED
ANSWERS) PLUS RATIONALES Q&A INSTANT DOWNLOAD PDF
140 QUESTIONS
TABLE OF CONTENTS
# TOPIC
1 Analyze and evaluate computer architecture and data representation
2 Apply advanced algorithms and data structures to solve computational problems
3 Assess operating system and network security principles
4 Synthesize database design and query optimization techniques
5 Critically evaluate system interoperability and emerging technologies
6 Air Force Electronic Data Processing Test
7 EDPT
8 Exam Practice Questions And Correct Answers
9 Verified Answers
10 Plus Rationales Q&A Instant Download Pdf
11 Foundations of Air Force Electronic Data Processing Test (EDPT)
12 Applied Air Force Electronic Data Processing Test (EDPT)
13 Advanced Air Force Electronic Data Processing Test (EDPT)
14 Air Force Electronic Data Processing Test (EDPT) Review
Page 1
,Q1 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In a real-time embedded system for avionics, a data race occurs between a
high-priority interrupt handler and a low-priority background task sharing a 32-bit
status register. Which synchronization primitive is most appropriate to ensure
atomicity without causing priority inversion or unbounded blocking?
A. Spinlock with disable interrupts
B. Mutex with priority inheritance
C. Non-blocking read-modify-write using atomic hardware instructions CORRECT
D. Semaphore with FIFO waiting queue
RATIONALE: Non-blocking atomic operations (e.g., CAS) avoid blocking and priority inversion,
ideal for short critical sections in real-time systems. Spinlocks can waste CPU and cause
inversion; mutexes and semaphores may block and cause inversion unless enhanced.
Q2 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
Given a relational schema R(A,B,C,D) with functional dependencies A->B, B->C,
and C->D, what is the highest normal form that R satisfies?
A. 1NF
B. 2NF CORRECT
C. 3NF
D. BCNF
RATIONALE: R has a transitive dependency A->B->C->D, so it violates 3NF. It is in 2NF because
the key is A (single attribute), and no partial dependency exists. BCNF requires every
determinant to be a candidate key, which is not the case.
Page 2
,Q3 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In TCP/IP networking, which mechanism allows a router to fragment an IPv6
packet?
A. The router uses the Fragment Offset field in the IPv6 header.
B. The router uses the Fragment Extension Header.
C. The router uses the Identification field and flags in the base header.
D. IPv6 routers do not fragment packets; fragmentation is done only by the source host.
CORRECT
RATIONALE: IPv6 routers do not perform fragmentation; only the source host can fragment using
extension headers. This simplifies router processing and relies on path MTU discovery. Options
A and C describe IPv4 mechanisms.
Q4 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
A cryptographic hash function H is used to ensure file integrity. An attacker finds
two distinct messages m1 and m2 such that H(m1) = H(m2). Which security
property is violated?
A. Preimage resistance
B. Second preimage resistance
C. Collision resistance CORRECT
D. Avalanche effect
RATIONALE: Finding any two distinct messages with the same hash violates collision resistance.
Second preimage resistance is about finding a different message with the same hash as a given
message; preimage resistance is about finding any message for a given hash. Avalanche effect
is not a security property but a diffusion property.
Page 3
, Q5 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
In a distributed database system, a transaction needs to be executed across
multiple nodes. Which isolation level ensures that the transaction sees a
consistent snapshot of the database as of the start of the transaction, even if other
transactions commit concurrently?
A. Read Committed
B. Repeatable Read
C. Serializable
D. Snapshot Isolation CORRECT
RATIONALE: Snapshot isolation provides each transaction with a consistent snapshot at start,
avoiding dirty reads and non-repeatable reads, but not all anomalies (e.g., write skew).
Serializable ensures full serializability but may block more. Read Committed allows
non-repeatable reads.
Q6 ANALYZE AND EVALUATE COMPUTER ARCHITECTURE AND DATA REPRESENTATION
Which of the following best describes the fundamental difference between RISC
and CISC instruction set architectures?
A. RISC has a larger number of instructions than CISC.
B. RISC instructions are generally executed in a single clock cycle, while CISC instructions may
take multiple cycles. CORRECT
C. CISC uses a load-store architecture, while RISC allows memory operands in arithmetic
instructions.
D. RISC uses microcode to implement complex instructions, while CISC uses hardwired control.
RATIONALE: RISC emphasizes simple, fixed-length instructions that can execute in one cycle,
with load-store architecture. CISC has complex instructions that may take multiple cycles and
often use microcode. Option C reverses the load-store property.
Page 4
