COP4600 FINAL EXAM 2026/2027 QUESTIONS AND
SOLUTIONS RATED A+
✔✔What info is available in an executable? - ✔✔Header, text, data, and symbols
✔✔Part of the executable which contains linkages (ex. library functions) - ✔✔Symbols
✔✔Part of the executable which contains basic info such as organization of the
executable itself - ✔✔Header
✔✔Which process segment contains pointers? - ✔✔Stack
✔✔What is stack/heap overflow? - ✔✔No space left between stack/heap
✔✔Why do context switches occur? - ✔✔Blocking operations, CPU yield operations,
CPU sharing, and asynchronous evemts
✔✔Examples of blocking operations which cause context switches - ✔✔IO and sleep
✔✔Examples of asynchronous events which cause context switches - ✔✔Hardware
interrupts, signals, and exceptions
✔✔What are signals? - ✔✔Software interrupts
✔✔What must the OS do during context switches - ✔✔Store register values, track
memory addresses, and update process state if necessary
✔✔When Device raises the signal line which is checked every instruction. The
hardware jumps to interrupt vector and a ______ has occured - ✔✔Hardware interrupt
✔✔T/F: Hardware interrupts can be ignored only in protected state - ✔✔True
✔✔What happens when a process receives a signal it is registered to catch - ✔✔1)
Kernel receives signal via system call
2) IF PCB has registered handler for the target, the signal is stored and the handler
queued
3) If there is no registered handler, the target is terminated
4) Normal function continues
✔✔What happens during a hardware interrupt? - ✔✔1) Device raise line
2) Controller sends interrupt
3) CPU asks interrupt
4) Controller sends IRQ#
,✔✔What hardware causes the trap to kernel mode? Responsible for the context switch,
looking up routine according to interrupt #, and changing the protection state -
✔✔Dispatcher (IRQ)
✔✔T/F: Signals are invoked by the kernel and process - ✔✔False
✔✔T/F: Signals involve a syscall - ✔✔True
✔✔T/F: On multicore systems, the interrupt controller can be programmed to send
different interrupts to different processor cores - ✔✔True
✔✔Why must hardware interrupts be super fast? - ✔✔They constantly happen and
prevent all processes from running
✔✔Location of the next instruction to execute after returning from a procedure call is
found in the _____ segment - ✔✔Stack
✔✔Constants are found in the what segment of a process? - ✔✔Data
✔✔Parameters passed to a procedure/method are located in the what segment of a
process? - ✔✔Stack
✔✔In what segment of a process can memory leaks occur? - ✔✔Heap
✔✔In what segment are global variables found? - ✔✔Data
✔✔Where are dynamically allocated variables located? - ✔✔Heap
✔✔Where are instructions to be executed located? - ✔✔Text
✔✔T/F: In batch systems, the user was the operator - ✔✔False
✔✔T/F: I/O-bound jobs underutilize the CPU in uniprogrammed systems - ✔✔True
✔✔T/F: A major motivation for multiprogramming batch systems was improving
resource utilization - ✔✔True
✔✔T/F: Memory protection was not needed in uniprogramming batch systems -
✔✔True
✔✔T/F: Batch systems had to implement multiprogramming - ✔✔False
, ✔✔T/F: Stack and heap allocation always happens when an OS handles an interrupt? -
✔✔False
✔✔What happens whenever an OS must handle an interrupt? - ✔✔PC is stored, CPU
registers are stored, and ISR is invoked
✔✔In a ______, hardware and system tasks are in kernel space - ✔✔Microkernel
✔✔In a ______, hardware, file system, and device drivers are in kernel space -
✔✔Monolithic kernel
✔✔Can an interrupt be interrupted? - ✔✔Yes
✔✔Hardware mechanism which prevents and sets the hierarchy of interrupts -
✔✔Interrupt mask
✔✔Interrupt with 4 specific qualities:
1) PC saved in a known state
2) All instructions PC were fully executed
3) No instructions after the PC have been executed
4) Execution state of PC instruction is known - ✔✔Precise interrupt
✔✔In a _________ interrupt, the instruction will finish execution before the interrupt is
serviced - ✔✔Precise
✔✔Interrupt when instructions are left incomplete/partially executed - ✔✔Imprecise
interrupts
✔✔T/F: We can always get a precise by rolling back incomplete instructions - ✔✔Not
always
✔✔Three types of schedulers - ✔✔Admission, memory, and CPU
✔✔Scheduler which decides which and when a job runs. Deals with queued data/tasks.
Long-term scheduler - ✔✔Admission
✔✔Scheduler which decides which jobs to swap in/out of main memory. Deals with user
interaction. Medium term scheduler - ✔✔Memory
✔✔Scheduler which decides which ready process runs next. Usually only pulls from
RAM. Short-term scheduler - ✔✔CPU
SOLUTIONS RATED A+
✔✔What info is available in an executable? - ✔✔Header, text, data, and symbols
✔✔Part of the executable which contains linkages (ex. library functions) - ✔✔Symbols
✔✔Part of the executable which contains basic info such as organization of the
executable itself - ✔✔Header
✔✔Which process segment contains pointers? - ✔✔Stack
✔✔What is stack/heap overflow? - ✔✔No space left between stack/heap
✔✔Why do context switches occur? - ✔✔Blocking operations, CPU yield operations,
CPU sharing, and asynchronous evemts
✔✔Examples of blocking operations which cause context switches - ✔✔IO and sleep
✔✔Examples of asynchronous events which cause context switches - ✔✔Hardware
interrupts, signals, and exceptions
✔✔What are signals? - ✔✔Software interrupts
✔✔What must the OS do during context switches - ✔✔Store register values, track
memory addresses, and update process state if necessary
✔✔When Device raises the signal line which is checked every instruction. The
hardware jumps to interrupt vector and a ______ has occured - ✔✔Hardware interrupt
✔✔T/F: Hardware interrupts can be ignored only in protected state - ✔✔True
✔✔What happens when a process receives a signal it is registered to catch - ✔✔1)
Kernel receives signal via system call
2) IF PCB has registered handler for the target, the signal is stored and the handler
queued
3) If there is no registered handler, the target is terminated
4) Normal function continues
✔✔What happens during a hardware interrupt? - ✔✔1) Device raise line
2) Controller sends interrupt
3) CPU asks interrupt
4) Controller sends IRQ#
,✔✔What hardware causes the trap to kernel mode? Responsible for the context switch,
looking up routine according to interrupt #, and changing the protection state -
✔✔Dispatcher (IRQ)
✔✔T/F: Signals are invoked by the kernel and process - ✔✔False
✔✔T/F: Signals involve a syscall - ✔✔True
✔✔T/F: On multicore systems, the interrupt controller can be programmed to send
different interrupts to different processor cores - ✔✔True
✔✔Why must hardware interrupts be super fast? - ✔✔They constantly happen and
prevent all processes from running
✔✔Location of the next instruction to execute after returning from a procedure call is
found in the _____ segment - ✔✔Stack
✔✔Constants are found in the what segment of a process? - ✔✔Data
✔✔Parameters passed to a procedure/method are located in the what segment of a
process? - ✔✔Stack
✔✔In what segment of a process can memory leaks occur? - ✔✔Heap
✔✔In what segment are global variables found? - ✔✔Data
✔✔Where are dynamically allocated variables located? - ✔✔Heap
✔✔Where are instructions to be executed located? - ✔✔Text
✔✔T/F: In batch systems, the user was the operator - ✔✔False
✔✔T/F: I/O-bound jobs underutilize the CPU in uniprogrammed systems - ✔✔True
✔✔T/F: A major motivation for multiprogramming batch systems was improving
resource utilization - ✔✔True
✔✔T/F: Memory protection was not needed in uniprogramming batch systems -
✔✔True
✔✔T/F: Batch systems had to implement multiprogramming - ✔✔False
, ✔✔T/F: Stack and heap allocation always happens when an OS handles an interrupt? -
✔✔False
✔✔What happens whenever an OS must handle an interrupt? - ✔✔PC is stored, CPU
registers are stored, and ISR is invoked
✔✔In a ______, hardware and system tasks are in kernel space - ✔✔Microkernel
✔✔In a ______, hardware, file system, and device drivers are in kernel space -
✔✔Monolithic kernel
✔✔Can an interrupt be interrupted? - ✔✔Yes
✔✔Hardware mechanism which prevents and sets the hierarchy of interrupts -
✔✔Interrupt mask
✔✔Interrupt with 4 specific qualities:
1) PC saved in a known state
2) All instructions PC were fully executed
3) No instructions after the PC have been executed
4) Execution state of PC instruction is known - ✔✔Precise interrupt
✔✔In a _________ interrupt, the instruction will finish execution before the interrupt is
serviced - ✔✔Precise
✔✔Interrupt when instructions are left incomplete/partially executed - ✔✔Imprecise
interrupts
✔✔T/F: We can always get a precise by rolling back incomplete instructions - ✔✔Not
always
✔✔Three types of schedulers - ✔✔Admission, memory, and CPU
✔✔Scheduler which decides which and when a job runs. Deals with queued data/tasks.
Long-term scheduler - ✔✔Admission
✔✔Scheduler which decides which jobs to swap in/out of main memory. Deals with user
interaction. Medium term scheduler - ✔✔Memory
✔✔Scheduler which decides which ready process runs next. Usually only pulls from
RAM. Short-term scheduler - ✔✔CPU
