Computer Architecture & Organization
Exam 2026/2027 | 80 Practice Questions
with Answers | Processor Design,
Pipelining, Memory Hierarchy & Parallel
Computing | University-Level Study Guide
Description:
Master computer architecture with this comprehensive 2026/2027 examination paper
covering processor design, pipelining, memory hierarchy, ARMv8, parallel computing,
and virtual memory. Features 80 multiple-choice questions with detailed explanations
for each answer. Ideal for final exam preparation, placement tests, and academic assessment.
Download now and boost your scores with verified 2026/2027 curriculum-aligned content!
, Computer Architecture Exam 2026/2027: 80 Questions &
Answers
SECTION A: PROCESSOR ARCHITECTURE AND INSTRUCTION SETS
(20 Marks)
Question 1
The abstract interface between hardware and the lowest-level software that encompasses all
information necessary to write a machine language program that will run correctly is known
as:
A) Application Binary Interface
B) System Software
C) Instruction Set Architecture
D) Microarchitecture
Answer: C
Explanation: The Instruction Set Architecture (ISA) serves as the fundamental contract
between hardware and software, defining instructions, registers, memory access mechanisms,
and I/O operations.
Question 2
Which of the following best describes the LEGv8 register architecture and its performance
implications?
A) 32 registers of 32 bits each, with larger register files always resulting in faster clock
frequencies
B) 31 registers of 64 bits each, where increasing register count always improves performance
C) 32 registers of 64 bits each, where more registers may lead to slower clock frequencies
due to signal propagation
D) 64 registers of 32 bits each, optimized for maximum parallel execution
Answer: C
Explanation: LEGv8 utilizes 32 registers, each 64 bits wide, and the principle "smaller is
faster" applies here because increasing the number of registers can lengthen signal paths,
potentially increasing clock cycle time.
,Question 3
In a load-store architecture, which statement accurately describes data transfer mechanisms?
A) All operations can directly access memory operands without restriction
B) Data memory may only be accessed via explicit load and store instructions
C) Accumulator registers hold all operands during arithmetic operations
D) Stack operations automatically handle all data movement
Answer: B
Explanation: Load-store architectures restrict data memory access to explicit load and store
instructions, with all arithmetic and logical operations requiring operands in registers.
Question 4
The instruction "SUBI" in LEGv8 performs which operation?
A) Subtract a register value from another register value
B) Subtract an immediate value from a register value
C) Store a value to memory with indexing
D) Subtract with carry from a register
Answer: B
Explanation: SUBI is the subtract immediate instruction in LEGv8, which subtracts a
constant value from a register's contents and stores the result in a destination register.
Question 5
What is the purpose of the Exception Syndrome Register (ESR) in ARMv8 architecture?
A) To store the current program counter value during normal execution
B) To record the cause of an exception for handling and debugging
C) To cache frequently used address translations
D) To manage power consumption during idle states
Answer: B
Explanation: The Exception Syndrome Register captures the specific reason for an
exception occurrence, providing crucial information for the exception handler to determine
appropriate recovery actions.
, SECTION B: PIPELINING AND HAZARD MANAGEMENT
(20 Marks)
Question 6
In a five-stage pipeline consisting of IF, ID, EX, MEM, and WB stages, what is the primary
characteristic of a pipeline stall?
A) The pipeline operates at maximum throughput with no latency
B) An instruction cannot proceed to the next stage due to a hazard, causing a bubble
C) All pipeline stages execute simultaneously without synchronization
D) The pipeline can process instructions in any arbitrary order
Answer: B
Explanation: A pipeline stall, also known as a bubble, occurs when an instruction cannot
advance to the next stage due to a hazard condition, effectively delaying instruction
processing while maintaining correctness.
Question 7
Forwarding, also known as bypassing, is a technique used to resolve which type of pipeline
hazard?
A) Structural hazards
B) Data hazards
C) Control hazards
D) Branch prediction errors
Answer: B
Explanation: Forwarding resolves data hazards by routing results directly from internal
pipeline buffers to subsequent instructions before the results are written to the programmer-
visible register file.
Exam 2026/2027 | 80 Practice Questions
with Answers | Processor Design,
Pipelining, Memory Hierarchy & Parallel
Computing | University-Level Study Guide
Description:
Master computer architecture with this comprehensive 2026/2027 examination paper
covering processor design, pipelining, memory hierarchy, ARMv8, parallel computing,
and virtual memory. Features 80 multiple-choice questions with detailed explanations
for each answer. Ideal for final exam preparation, placement tests, and academic assessment.
Download now and boost your scores with verified 2026/2027 curriculum-aligned content!
, Computer Architecture Exam 2026/2027: 80 Questions &
Answers
SECTION A: PROCESSOR ARCHITECTURE AND INSTRUCTION SETS
(20 Marks)
Question 1
The abstract interface between hardware and the lowest-level software that encompasses all
information necessary to write a machine language program that will run correctly is known
as:
A) Application Binary Interface
B) System Software
C) Instruction Set Architecture
D) Microarchitecture
Answer: C
Explanation: The Instruction Set Architecture (ISA) serves as the fundamental contract
between hardware and software, defining instructions, registers, memory access mechanisms,
and I/O operations.
Question 2
Which of the following best describes the LEGv8 register architecture and its performance
implications?
A) 32 registers of 32 bits each, with larger register files always resulting in faster clock
frequencies
B) 31 registers of 64 bits each, where increasing register count always improves performance
C) 32 registers of 64 bits each, where more registers may lead to slower clock frequencies
due to signal propagation
D) 64 registers of 32 bits each, optimized for maximum parallel execution
Answer: C
Explanation: LEGv8 utilizes 32 registers, each 64 bits wide, and the principle "smaller is
faster" applies here because increasing the number of registers can lengthen signal paths,
potentially increasing clock cycle time.
,Question 3
In a load-store architecture, which statement accurately describes data transfer mechanisms?
A) All operations can directly access memory operands without restriction
B) Data memory may only be accessed via explicit load and store instructions
C) Accumulator registers hold all operands during arithmetic operations
D) Stack operations automatically handle all data movement
Answer: B
Explanation: Load-store architectures restrict data memory access to explicit load and store
instructions, with all arithmetic and logical operations requiring operands in registers.
Question 4
The instruction "SUBI" in LEGv8 performs which operation?
A) Subtract a register value from another register value
B) Subtract an immediate value from a register value
C) Store a value to memory with indexing
D) Subtract with carry from a register
Answer: B
Explanation: SUBI is the subtract immediate instruction in LEGv8, which subtracts a
constant value from a register's contents and stores the result in a destination register.
Question 5
What is the purpose of the Exception Syndrome Register (ESR) in ARMv8 architecture?
A) To store the current program counter value during normal execution
B) To record the cause of an exception for handling and debugging
C) To cache frequently used address translations
D) To manage power consumption during idle states
Answer: B
Explanation: The Exception Syndrome Register captures the specific reason for an
exception occurrence, providing crucial information for the exception handler to determine
appropriate recovery actions.
, SECTION B: PIPELINING AND HAZARD MANAGEMENT
(20 Marks)
Question 6
In a five-stage pipeline consisting of IF, ID, EX, MEM, and WB stages, what is the primary
characteristic of a pipeline stall?
A) The pipeline operates at maximum throughput with no latency
B) An instruction cannot proceed to the next stage due to a hazard, causing a bubble
C) All pipeline stages execute simultaneously without synchronization
D) The pipeline can process instructions in any arbitrary order
Answer: B
Explanation: A pipeline stall, also known as a bubble, occurs when an instruction cannot
advance to the next stage due to a hazard condition, effectively delaying instruction
processing while maintaining correctness.
Question 7
Forwarding, also known as bypassing, is a technique used to resolve which type of pipeline
hazard?
A) Structural hazards
B) Data hazards
C) Control hazards
D) Branch prediction errors
Answer: B
Explanation: Forwarding resolves data hazards by routing results directly from internal
pipeline buffers to subsequent instructions before the results are written to the programmer-
visible register file.
