Computer Architecture
Performance, Pipelining, Assembly & Memory
Computer Organization & Architecture | Undergraduate CS
Questions & Verified Answers
, 25 questions covering Amdahl's Law, CPU time, pipeline hazards, assembly, IEEE 754, cache, and
parallel processing.
Q1. What is Amdahl's Law and what is its formula?
Answer: Speedup = 1 / [(1 - P) + (P / S)], where P is the fraction of the program that can be
parallelized and S is the speedup of that parallelizable portion.
Key insight: the non-parallelizable fraction (1-P) is the bottleneck.
As S approaches infinity, the maximum speedup approaches 1/(1-P).
Example: if 90% of a program is parallelized (P=0.9) and S=10, speedup = 1/(0.1+0.09) ≈ 5.26×
Q2. What is the CPU Time formula?
Answer: CPU Time = Instruction Count × CPI × Clock Cycle Time, or equivalently: CPU Time
= IC × CPI / Clock Frequency.
IC = number of instructions executed
CPI = average clock cycles per instruction
To improve performance: reduce IC, reduce CPI, or increase clock frequency
Q3. What are the three types of pipeline hazards?
Answer: Structural hazards (resource conflict), data hazards (instruction dependency, most
commonly RAW — Read After Write), and control hazards (branch instructions causing
uncertainty about the next fetch).
Structural: solved by stalling or duplicating hardware.
Data (RAW): solved by forwarding/bypassing or inserting NOP stalls.
Control: solved by branch prediction (static/dynamic) or delayed branching.
Q4. Given $t0 = 0xAAAAAAAA, what is $t2 after: srl $t2, $t0, 3 then andi $t2, $t2, 0xFFFF?
Answer: $t2 = 0x00005555
Step 1 — srl $t2, $t0, 3: logical right shift 0xAAAAAAAA by 3 bits.
0xAAAAAAAA binary = 1010 1010 ... (repeating). Shift right 3: 0x15555555
Step 2 — andi $t2, $t2, 0xFFFF: AND with 0x0000FFFF keeps only lower 16 bits.
0x15555555 AND 0x0000FFFF = 0x00005555
Q5. For the C code float f2c(float fahr){ return ((5.0/9.0)*(fahr-32.0)); }, what is the next instruction
compiled by an optimized compiler assuming all constants are already loaded?
A. muls $f0, $f16, $f18
B. sub.s $f18, $f12, $f18
C. lwcl $f18, const32($gp)
D. div.s $f16, $f16, $f18
Answer: B. sub.s $f18, $f12, $f18
The formula requires fahr-32.0 before multiplication.
Since all constants are already loaded, the optimized compiler computes the subtraction first.
sub.s is the MIPS single-precision floating-point subtraction instruction.
Q6. Calculate (8.33×10¹) + (3.87×10⁰) with 3 significant decimal digits. With guard/round digits vs
without — by how many ulp do the answers differ?
Answer: 1
Exact sum: 83.3 + 3.87 = 87.17
With guard and round digits: round to 3 significant digits → 87.2 (digit after 3rd is 7 ≥ 5, round up)
Performance, Pipelining, Assembly & Memory
Computer Organization & Architecture | Undergraduate CS
Questions & Verified Answers
, 25 questions covering Amdahl's Law, CPU time, pipeline hazards, assembly, IEEE 754, cache, and
parallel processing.
Q1. What is Amdahl's Law and what is its formula?
Answer: Speedup = 1 / [(1 - P) + (P / S)], where P is the fraction of the program that can be
parallelized and S is the speedup of that parallelizable portion.
Key insight: the non-parallelizable fraction (1-P) is the bottleneck.
As S approaches infinity, the maximum speedup approaches 1/(1-P).
Example: if 90% of a program is parallelized (P=0.9) and S=10, speedup = 1/(0.1+0.09) ≈ 5.26×
Q2. What is the CPU Time formula?
Answer: CPU Time = Instruction Count × CPI × Clock Cycle Time, or equivalently: CPU Time
= IC × CPI / Clock Frequency.
IC = number of instructions executed
CPI = average clock cycles per instruction
To improve performance: reduce IC, reduce CPI, or increase clock frequency
Q3. What are the three types of pipeline hazards?
Answer: Structural hazards (resource conflict), data hazards (instruction dependency, most
commonly RAW — Read After Write), and control hazards (branch instructions causing
uncertainty about the next fetch).
Structural: solved by stalling or duplicating hardware.
Data (RAW): solved by forwarding/bypassing or inserting NOP stalls.
Control: solved by branch prediction (static/dynamic) or delayed branching.
Q4. Given $t0 = 0xAAAAAAAA, what is $t2 after: srl $t2, $t0, 3 then andi $t2, $t2, 0xFFFF?
Answer: $t2 = 0x00005555
Step 1 — srl $t2, $t0, 3: logical right shift 0xAAAAAAAA by 3 bits.
0xAAAAAAAA binary = 1010 1010 ... (repeating). Shift right 3: 0x15555555
Step 2 — andi $t2, $t2, 0xFFFF: AND with 0x0000FFFF keeps only lower 16 bits.
0x15555555 AND 0x0000FFFF = 0x00005555
Q5. For the C code float f2c(float fahr){ return ((5.0/9.0)*(fahr-32.0)); }, what is the next instruction
compiled by an optimized compiler assuming all constants are already loaded?
A. muls $f0, $f16, $f18
B. sub.s $f18, $f12, $f18
C. lwcl $f18, const32($gp)
D. div.s $f16, $f16, $f18
Answer: B. sub.s $f18, $f12, $f18
The formula requires fahr-32.0 before multiplication.
Since all constants are already loaded, the optimized compiler computes the subtraction first.
sub.s is the MIPS single-precision floating-point subtraction instruction.
Q6. Calculate (8.33×10¹) + (3.87×10⁰) with 3 significant decimal digits. With guard/round digits vs
without — by how many ulp do the answers differ?
Answer: 1
Exact sum: 83.3 + 3.87 = 87.17
With guard and round digits: round to 3 significant digits → 87.2 (digit after 3rd is 7 ≥ 5, round up)
