VLSI Digital Design (ENGG 4550) | Engineering: ENGG4550_Midterm_Solution_2026.

NAME:
ID:

UNIVERSITY OF GUELPH
School of Engineering
ENGG*4550: VLSI Digital Design
Instructor: Haleh Vahedi
Midterm Exam
Feb. 24,2026, 10 am. - 11 a.m.
Weight: 30%
Time: 1.0 hour
Type: closed book. Formula sheet has been
provided.
Aid: Simple scientific calculator.

Instructions:
e Write your name and student ID first.
* Answer all the questions in any order and clearly
state any assumptions you make.
¢ Show your steps and present a clean and organized
solution for ful] mark.
* Explain the circuits and calculations you derive.




Problem # Marks
1[5 marks]
2[4 marks]
3[4 marks]
4 [ 6 marks]
5 [ 5 marks]
6 [ 6 marks]

Total: 30




ENGG*4550: VLSI Digital Design. Midt
erm Exam Winter 2026
Page 1 of 9

, NAME:
ID:

PROBLEM 1 [5 marks]|
Sketch a transistor-level schematic for a static CMOS logic
gate that implements the following
function:

Y=(AC+B) D
Explain your design.
=




(A C~+L> AJM
)C) U ” C.! O He'f’wa( e 5 §~u~u = a\ 1 =y =3 \"1
¥

. | sy _ r Y7
1S Ui el laVerSien” Symbo| (1
Y .

of v )
I qflf‘p'
r
¢ ,2‘2
{ ;»"‘; nNe ‘Liszr"».
i N
'S (Cn /b (e ’
r ENGG* '4550 VLSI Digital Design. Midterm Exam Wmter 2026
Page 2 of 9