EEE 304 FINAL TEST 2026 QUESTIONS
WITH CORRECT ANSWERS GRADED A+
◍ Build an 8:1 MUX using vector indexing.
Answer: // alternate 8:1 MUXmodule mux8a ( input [7:0] a, input [2:0] s,
output z); assign z = a[s];endmodule
◍ For single processing, would you use FPGAs or MCUs?.
Answer: FPGAs
◍ Which uses more power, FPGAs or MCUs?.
Answer: FPGAs
◍ Which costs more, FPGAs or MCUs?.
Answer: FPGAs
◍ Write a SystemVerilog module that counts from 0 to Maxval and generates
a one-cycle pulse ClkOut when the counter resets..
Answer: module clocktime_f( input clk, Freerun, Reset, input [7:0] Maxval,
output reg [7:0] Count, output reg ClkOut);always_ff @(posedge clk or
posedge Reset) begin if (Reset) begin Count <= 0; ClkOut <= 0; end else if
(freerun) if (Count < Maxval) begin Count <= Count + 8'd1; ClkOut <=
1'b0; end else begin Count <= 8'd0; ClkOut <= 1'b1; endendendmodule
◍ What does this statement do? casez (sel) 4'b010z : statement;endcase.
Answer: It executes statement whenever sel has its upper three bits equal to
010, regardless of whether the least significant bit is 0 or 1 (i.e., for 4'b0100
or 4'b0101).
◍ Create a SystemVerilog module hoursmsb_tester that uses a function with a
loop to determine the tens digit of an 8-bit value H, then computes the ones
digit..
Answer: // module for testing function// for H=8'd59 for instance Hh=5 and
, Hl=9// should be able to drop function into your codemodule
hoursmsb_tester(input [7:0] H, output reg [7:0] Hh, Hl);// function returning
high order bit for hourfunction [7:0] hourmsb; input [7:0] A; integer i;
hourmsb = 0; for (i = 0; i <= 9; i = i + 1) if (A >= (hourmsb*8'd10 + 8'd9))
hourmsb = hourmsb + 8'd1;endfunction// always loop that executes this
function and calculation of Hlalways @(*)begin Hh = hourmsb(H); Hl = H -
Hh * 10;endendmodule
◍ Why do we want to avoid nested if statements?.
Answer: They are serial and tend to synthesize to unnecessarily serial
topoloies that cause timing errors with propagaion delays
◍ With this code, what happens if 110 is the input? module uniquecasez (
input [2:0] irq, output logic out1, out2, out3); always_comb begin out1 =
1'b0; out2 = 1'b0; out3 = 1'b0; unique casez (irq) 3'b1?? : out3 = 1'b1; 3'b?1?
: out2 = 1'b1; 3'b??1 : out1 = 1'b1; endcase endendmodule.
Answer: An error occurs because it matches both the cases for out 3 and out
2
◍ In signed arithmetic, what bit is used for the sign?.
Answer: The highest order bit
◍ Are priority encoders series or parallel?.
Answer: Series
◍ Do MCUs use parallel or serial execution?.
Answer: serial
◍ When using the keyword unique, are all the cases evaluated in series or
parallel?.
Answer: Parallel. Since they can never overlap, the tool does not need
priority logic. Instead, it can build:Separate comparison logic for each case
itemAll comparisons exist at the same timeNo "first wins" chain needed
◍ What does this do? {Rtemp, R} = A * B; given A and B are 8 bit signed
numbers.
Answer: Their product is 16 bits.{Rtemp, R} splits the 16-bit result
WITH CORRECT ANSWERS GRADED A+
◍ Build an 8:1 MUX using vector indexing.
Answer: // alternate 8:1 MUXmodule mux8a ( input [7:0] a, input [2:0] s,
output z); assign z = a[s];endmodule
◍ For single processing, would you use FPGAs or MCUs?.
Answer: FPGAs
◍ Which uses more power, FPGAs or MCUs?.
Answer: FPGAs
◍ Which costs more, FPGAs or MCUs?.
Answer: FPGAs
◍ Write a SystemVerilog module that counts from 0 to Maxval and generates
a one-cycle pulse ClkOut when the counter resets..
Answer: module clocktime_f( input clk, Freerun, Reset, input [7:0] Maxval,
output reg [7:0] Count, output reg ClkOut);always_ff @(posedge clk or
posedge Reset) begin if (Reset) begin Count <= 0; ClkOut <= 0; end else if
(freerun) if (Count < Maxval) begin Count <= Count + 8'd1; ClkOut <=
1'b0; end else begin Count <= 8'd0; ClkOut <= 1'b1; endendendmodule
◍ What does this statement do? casez (sel) 4'b010z : statement;endcase.
Answer: It executes statement whenever sel has its upper three bits equal to
010, regardless of whether the least significant bit is 0 or 1 (i.e., for 4'b0100
or 4'b0101).
◍ Create a SystemVerilog module hoursmsb_tester that uses a function with a
loop to determine the tens digit of an 8-bit value H, then computes the ones
digit..
Answer: // module for testing function// for H=8'd59 for instance Hh=5 and
, Hl=9// should be able to drop function into your codemodule
hoursmsb_tester(input [7:0] H, output reg [7:0] Hh, Hl);// function returning
high order bit for hourfunction [7:0] hourmsb; input [7:0] A; integer i;
hourmsb = 0; for (i = 0; i <= 9; i = i + 1) if (A >= (hourmsb*8'd10 + 8'd9))
hourmsb = hourmsb + 8'd1;endfunction// always loop that executes this
function and calculation of Hlalways @(*)begin Hh = hourmsb(H); Hl = H -
Hh * 10;endendmodule
◍ Why do we want to avoid nested if statements?.
Answer: They are serial and tend to synthesize to unnecessarily serial
topoloies that cause timing errors with propagaion delays
◍ With this code, what happens if 110 is the input? module uniquecasez (
input [2:0] irq, output logic out1, out2, out3); always_comb begin out1 =
1'b0; out2 = 1'b0; out3 = 1'b0; unique casez (irq) 3'b1?? : out3 = 1'b1; 3'b?1?
: out2 = 1'b1; 3'b??1 : out1 = 1'b1; endcase endendmodule.
Answer: An error occurs because it matches both the cases for out 3 and out
2
◍ In signed arithmetic, what bit is used for the sign?.
Answer: The highest order bit
◍ Are priority encoders series or parallel?.
Answer: Series
◍ Do MCUs use parallel or serial execution?.
Answer: serial
◍ When using the keyword unique, are all the cases evaluated in series or
parallel?.
Answer: Parallel. Since they can never overlap, the tool does not need
priority logic. Instead, it can build:Separate comparison logic for each case
itemAll comparisons exist at the same timeNo "first wins" chain needed
◍ What does this do? {Rtemp, R} = A * B; given A and B are 8 bit signed
numbers.
Answer: Their product is 16 bits.{Rtemp, R} splits the 16-bit result
