Test Bank for Digital Fundamentals 11th Edition by Thomas Floyd||ISBN:9780132737968

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Test Bank for Digital
Fundamentals, 11e
Thomas Floyd (All
Chapters,)

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Chapter 1

Name


MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the
question.
1) Which circuit converts data from serial form to parallel form? 1)
A) Multiplexer B) Comparator C) Encoder D) Demultiplexer

2) Which one of the circuits listed is made up of flip-flops? 2)
A) A comparator B) A converter C) A register D) A multiplexer

3) The time from one leading edge on a digital waveform to the next is the waveform . 3)
A) rise time B) pulse width C) period D) fall time




Figure 1-1

4) The time between transition 1 and transition 3 in Figure 1-1 is the . 4)
A) period B) frequency C) amplitude D) pulse width

5) The output from an OR gate is HIGH . 5)
A) when at least one input is HIGH B) only when all inputs are HIGH
C) only when all inputs are LOW D) none of the above




Figure 1-3

6) The symbol in Figure 1-3(B) represents the function. 6)
A) OR B) NON C) XOR D) AND

7) On a positive-going pulse, the leading edge is the . 7)
A) HIGH-to-LOW transition B) falling edge
C) negative-going edge D) positive-going edge

8) Of the circuits listed, the one that is most likely to be found in a CD player is a(n) . 8)
A) programmable logic device B) digital-to-analog converter
C) analog-to-digital converter D) SPLD




Figure 1-1

9) Which edge in Figure 1-1 is the trailing edge? 9)

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A) 1 B) 2 C) 3 D) Both 1 and 3

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10) The arrow in the figure below points to pin . 10)




A) 17 B) 16 C) 5 D) 4

11) On a negative-going pulse, the leading edge is the . 11)
A) LOW-to-HIGH transition B) negative-going edge
C) positive-going edge D) rising edge

12) Which circuit converts coded information into a noncoded form? 12)
A) Comparator B) Encoder C) Decoder D) Multiplexer




Figure 1-3

13) The symbol in Figure 1-3(C) represents the function. 13)
A) XOR B) NOT C) OR D) AND

14) The approximate duty cycle for the digital waveform below is . 14)



A) 20% B) 80% C) 30% D) 50%




Figure 1-4

15) The package style in Figure 1-4(C) is a(n) . 15)
A) SOIC B) PLCC C) LCCC D) FP

16) The output from an OR gate is LOW . 16)
A) only when all inputs are LOW B) whenever any input is HIGH
C) only when all inputs are HIGH D) none of the above

17) The netlist is generated during the phase of the PLD programming process. 17)
A) design entry B) compilation C) synthesis D) download