UMBC IS 310 Exam 2 2026 (400+ Questions) – Computer Architecture, Networking Protocols, I/O Systems, Caching, Compression & Multimedia Q&A

This document contains over 400 fully answered exam questions for UMBC IS 310 Exam 2 2026, covering advanced topics in computer architecture, system buses, I/O devices, networking protocols, communication theory, multimedia systems, caching, compression, and software development tools. The material includes detailed concepts such as symbolic debugging using symbol tables and memory maps, Java bytecode and JVM execution, native versus interpreted applications, integrated development environments (IDEs), and compiler libraries. It also explains CPU caching mechanisms including cache hits, cache misses, cache controllers, write operations, and performance optimization through buffering and caching. The study guide provides in-depth coverage of communication systems and networking principles including TCP/IP model layers, sockets (IP address plus port number), encapsulation, logical versus physical topology, IEEE 802 standards, CSMA/CA ready-to-send signaling, packet switching, circuit switching inefficiencies, FDM and wavelength-division multiplexing, multilevel coding, parity (even and odd), attenuation, electromagnetic interference, noise, jitter in VoIP systems, and guided transmission over copper or fiber. It distinguishes dotted decimal notation (IPv4) and colon hexadecimal notation (IPv6), and explains routers making forwarding decisions using Layer 3 addresses. Extensive multimedia and I/O device topics include laser printers using electrical charge attraction, photosensors in digital cameras, mark and pattern sensors, bar-code scanners with scanning lasers, DAC (digital-to-analog converters), carrier waves, refresh cycles in displays, active matrix displays, OLED characteristics (thin, bright, low power), touchscreen TFT capacitance detection, dithering and grayscale halftoning, image resolution measured in DPI, and compression techniques (lossless vs lossy, compression ratio). Sound fundamentals such as phonemes, continuous speech, monophonic output, and sine wave transmission are also addressed. Hardware and system-level topics include system buses divided into data, address, control, and power buses; Peripheral Component Interconnect (PCI); external I/O buses such as USB; multiple-processor architecture; multicore scaling; digital signal processors (DSPs); InfiniBand high-speed communication architecture; serial versus asynchronous transmission; square wave transmission over short distances; and peripheral device coordination via the control bus. This document is particularly relevant for: UMBC IS 310 students preparing for Exam 2 Undergraduate students studying Computer Architecture and Networking Information Systems majors reviewing communication protocols Students preparing for systems implementation and infrastructure exams IT and MIS students studying multimedia systems and I/O architecture It is suitable for courses such as: Computer Architecture and Organization II Data Communications and Networking Operating Systems and I/O Systems Systems Programming and Debugging Multimedia Systems and Digital Media Processing Keywords: UMBC IS 310 exam 2 2026, symbolic debugger symbol table memory map, Java bytecode JVM execution, cache hit cache miss controller, TCP IP model layers, socket IP address port number, IPv4 dotted decimal IPv6 colon hexadecimal, packet switching vs circuit switching, FDM wavelength division multiplexing, parity even odd error detection, attenuation electromagnetic interference noise, jitter VoIP silence overlap, compression ratio lossless vs lossy, OLED thin bright low power, digital to analog converter DAC, active matrix display TFT touchscreen, PCI peripheral component interconnect, IEEE 802 standards networking, multiple processor architecture scaling up, InfiniBand high speed architecture