CYBR 3123 TEST 2 QUESTIONS AND 100% CORRECT ANSWERS
LATEST VERSION
It is necessary to translate the address produced by the CPU into a cache
location. ANSWER Cache mapping is required due to:
Volatile- ANSWER What feature of random-access memory renders it unfit for
long-term storage?
external, internal- ANSWER Memory segmentation may cause ___
fragmentation, whereas paging may cause ___ fragmentation.
of the locality or concept, ANSWER Cache memory works well because
RAM- ANSWER ___ memory makes it simple and quick to write to and read
from data.
ANSWER for the CPU and RAM Usually, cache memory is located between:
where the needed data is located in the cache block: ANSWER A main
memory address's offset field is used to ascertain:
If two or more blocks that map to the exact place are used alternately, their
performance will suffer. ANSWER Direct mapped cache's simplicity and ease
of implementation are two of its main advantages. Direct mapped cache's
primary drawback is:
, to save page table data in a cache - ANSWER TLB's objective is ___.
thrashing- ANSWER Every algorithm listed below is a cache replacement
algorithm, with the exception of:
True- ANSWER : Every process on a computer that is paging needs to have a
table.
ANSWER Cache replacement policies are required in order to identify which
cache block should be the victim block:
True— ANSWER Knowing whether a computer is byte or word addressable is
crucial because, when performing cache mapping, we need to know how many
addresses are in the main memory, cache, and each block.
Indeed, a cache that stores both data and instructions is called a unified cache.
hit- ANSWER When the necessary information is stored at a specific memory
level, we refer to this as a:
ROM is read-only, but RAM is read-write. ANSWER RAM and ROM
memory differ primarily in the following ways:
Five bits for the offset and three bits for the page. The virtual address format is
as follows, assuming an 8-bit virtual address with 32-byte pages:
Which form of memory has the longest (slowest) access time among secondary
memory?
True: Direct mapping has a set size of 1 and is a set associative mapping.
LATEST VERSION
It is necessary to translate the address produced by the CPU into a cache
location. ANSWER Cache mapping is required due to:
Volatile- ANSWER What feature of random-access memory renders it unfit for
long-term storage?
external, internal- ANSWER Memory segmentation may cause ___
fragmentation, whereas paging may cause ___ fragmentation.
of the locality or concept, ANSWER Cache memory works well because
RAM- ANSWER ___ memory makes it simple and quick to write to and read
from data.
ANSWER for the CPU and RAM Usually, cache memory is located between:
where the needed data is located in the cache block: ANSWER A main
memory address's offset field is used to ascertain:
If two or more blocks that map to the exact place are used alternately, their
performance will suffer. ANSWER Direct mapped cache's simplicity and ease
of implementation are two of its main advantages. Direct mapped cache's
primary drawback is:
, to save page table data in a cache - ANSWER TLB's objective is ___.
thrashing- ANSWER Every algorithm listed below is a cache replacement
algorithm, with the exception of:
True- ANSWER : Every process on a computer that is paging needs to have a
table.
ANSWER Cache replacement policies are required in order to identify which
cache block should be the victim block:
True— ANSWER Knowing whether a computer is byte or word addressable is
crucial because, when performing cache mapping, we need to know how many
addresses are in the main memory, cache, and each block.
Indeed, a cache that stores both data and instructions is called a unified cache.
hit- ANSWER When the necessary information is stored at a specific memory
level, we refer to this as a:
ROM is read-only, but RAM is read-write. ANSWER RAM and ROM
memory differ primarily in the following ways:
Five bits for the offset and three bits for the page. The virtual address format is
as follows, assuming an 8-bit virtual address with 32-byte pages:
Which form of memory has the longest (slowest) access time among secondary
memory?
True: Direct mapping has a set size of 1 and is a set associative mapping.
