Storage Technologies Review: Questions and Answers, Exams of Computer
Science
Registers hold most frequently used ____ - ANSWERdata
cache near CPU acts as staging area for relatively slow ____ ______ and ____
______ acts as a staging area for relatively slow ____ - ANSWERmain
memory; main memory; disk
bistable - ANSWERin an SRAM chip, a circuit can stay indefinitely in either of
2 voltage configurations or states, any other state will be unstable (move
towards either stable state)
Is the state/configuration in an SRAM permanently affected when there is a
disturbance? - ANSWERNo, circuit will return to stable value when
disturbance is removed
Is DRAM or SRAM sensitive to disturbance? - ANSWERDRAM
SRAM transistors/bit - ANSWER6
DRAM transistors/bit - ANSWER1
, SRAM relative access time - ANSWER1x
DRAM relative access time - ANSWER10x
Is SRAM or DRAM persistent? - ANSWERSRAM
SRAM relative cost - ANSWER100x
DRAM relative cost - ANSWER1x
What makes up for the fact that various sources of leakage can cause a DRAM
cell to lose its charge within a time period of 10-100 ms? - ANSWERComputer
that operate with clock cycle times measured in ns make this time period
relatively long enough for it not to happen when it would affect a process
Does SRAM or DRAM need to refresh? - ANSWERDRAM
Does SRAM or DRAM consume less power? - ANSWERDRAM
DRAM supercell - ANSWERDRAM is partitioned into d supercells containing w
DRAM cells
How many bits does a d*w DRAM store? - ANSWERd*w bits
How are supercells organized (shape)? - ANSWERrectangular array
Science
Registers hold most frequently used ____ - ANSWERdata
cache near CPU acts as staging area for relatively slow ____ ______ and ____
______ acts as a staging area for relatively slow ____ - ANSWERmain
memory; main memory; disk
bistable - ANSWERin an SRAM chip, a circuit can stay indefinitely in either of
2 voltage configurations or states, any other state will be unstable (move
towards either stable state)
Is the state/configuration in an SRAM permanently affected when there is a
disturbance? - ANSWERNo, circuit will return to stable value when
disturbance is removed
Is DRAM or SRAM sensitive to disturbance? - ANSWERDRAM
SRAM transistors/bit - ANSWER6
DRAM transistors/bit - ANSWER1
, SRAM relative access time - ANSWER1x
DRAM relative access time - ANSWER10x
Is SRAM or DRAM persistent? - ANSWERSRAM
SRAM relative cost - ANSWER100x
DRAM relative cost - ANSWER1x
What makes up for the fact that various sources of leakage can cause a DRAM
cell to lose its charge within a time period of 10-100 ms? - ANSWERComputer
that operate with clock cycle times measured in ns make this time period
relatively long enough for it not to happen when it would affect a process
Does SRAM or DRAM need to refresh? - ANSWERDRAM
Does SRAM or DRAM consume less power? - ANSWERDRAM
DRAM supercell - ANSWERDRAM is partitioned into d supercells containing w
DRAM cells
How many bits does a d*w DRAM store? - ANSWERd*w bits
How are supercells organized (shape)? - ANSWERrectangular array
