12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Science Computer Science Computer Architecture
Computer Science Paper 1
A register in the cpu that controls and coordinates the activities
Control Unit
of the cpu directing the flow of data
a series of connectors that transfer signals between internal
Bus
components
causes data from the addressed location in RAM to be placed on
Memory Read
the data bus
Causes data on the data bus to be written into the addressed
Memory Write
location.
Bus Request Indicates that a device is requesting the use of the data bus
Bus Grant Indicates that the CPU has granted access to the data bus.
System bus collective term for address, data and control bus
A bi-directional path for moving data and instructions between
Data bus
system components
Clock used to synchronize operations
A bi-directional bus to transmit command, timing and specific
Control bus
status information between system components
A one directional bus that transmits memory addresses that are
Address bus used as operands in programming instructions, so that data can
be retrieved from main memory
Arithmetic-Logic unit, preforms logical and arithmetic operations
on data
ALU
e.g. ADD, SUBTRACT, shift operations or Boolean logic
High speed memory cells, all arithmetic and logic happens in
Registers these, typically there are 16 general purpose registers in a CPU,
they are very fast
A special purpose register which stores the result of calculations
Accumulator
made by the ALU
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,12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Holds the address of the next instruction to be executed, this can
Program Counter (PC) be the next instruction in a sequence of instructions, or a branch/
jump
Current instruction register (CIR) stores the actual instruction that is being decoded
stores the address of instructions and data that need to be
Memory address register (MAR)
fetched from or sent to memory
Memory data register (MDR) stores the data which is to be sent or fetched from memory
Interrupt registers generates and detects interrupts
PC
MAR
Address Bus
Memory
Data bus
Fetch Decode Execute register
MDR
sequence
CIR
Decode Unit
MAR
Address Bus
Main Memory
- Instructions pulled from memory and stored in main memory.
- Program Counter (a register) stores the address location of the
instruction
Fetch phase
- Program Counter and instructions are placed in the Instruction
Register (IR)
- Program Counter is incremented by 1
1. Instruction in CIR is decoded
2. Instruction is split into opcode and operand
3. the operand determines the type of instruction
Decode phase - if its the address of the data used with the operation it is copied
into the MAR
- if it the actual data to be operated on it is copied into the MDR
4. the data to be operated on is passed into the ALU/ acc
The appropriate instruction/ opcode is carried out on the data/
Execute phase
operand
- Clock speed
Main factors affecting
- Number of cores
preformance
- The amount and type of cache
The system clock generates a series of signals (1 or 0)
Clock speed synchronising with the CPU operations. The CPU cannot preform
faster than the system clock.
Positives of increasing clock You can carry out more instructions in a given time; improved
speed performance
What is clock speed measured Hz
in?
Negatives of increasing clock more heat generated meaning computers must be cooled (either
speed with heat sync/fan or water/oil cooling)
Positive of multiple cores may speed processing as concurrency is available
complicated circuitry (more expensive)
negatives of multiple cores
doesn't always improve performance
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,12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Positives of increasing cache less time fetching data; improved performance
size
Negatives of increasing cache expensive, physically further from cpu and thus slower
size
Level 1 cache Small but extremely fast
Level 2 cache fairly fast and medium sized
Level 3 cache slower and bigger
When the computer architecture allows the next instruction to be
Pipelining fetched at the same time as the processor is preforming
arithmetic or logical operations. (buffer close to the processor)
The width of the address bus determines the maximum possible
capacity of the system
Bottleneck Address bus
e.g. is the address bus was 8 lines, the maximum it could transmit
would be 256
Bottleneck Data bus A wider bus can transmit larger values/ more bits per instruction
Instructions and data:
- Share memory
- Share bus system
Von Neumann architecture
- Stored in same format
- Same bit size for memory
- Single CPU and ALU
Instructions and data are:
- stored in separate memory units
Harvard architecture
- use separate bus systems
- allows for pipelining
Used extensively with embedded digital signal processing. The
Harvard architecture uses
two separate memories can have different characteristics
The general structure of the Von Neumann architecture used in
Von Neumann machine
most computers
Von Neumann:
- Used in conventional processors in PCs
- instructions and data share the same memory
- One bus
- Programs can be optimized in size
Comparison of Von Neumann
and Harvard architectures Harvard:
- Used in digital signal processing, embedded systems, mobile
communication
- Instructions and data held in separate memories
- Parallel data and instruction buses may be used
- Programs tend to be large
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, 12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Modern high-performance CPU chips incorporate aspects of
both Von Neumann and Harvard architectures
Contemporary processor
architectures
e.g. memory for both data and instructions but cache is divided
into instruction and data and multiple parallel data buses
Complex instruction set computing, large number of instruction
CISC
each taking multiple machine cycles to carry out.
a single chip which contains 2 or more independent CPUs which
Chip Multi Processor
can execute independent instructions
Many specialized instructions had to be built into the hardware
even though about 20% will be used in the average program
more complex circuitry/hardware
Single machine instruction takes multiple machine cycles to carry
Disadvantage of CISC out
greater energy consumption
can't support pipelining
more silicon require to make
physically larger in size
compiler has to do very little work to translate high level
language to machine code
Advantage of CISC
because code is relatively short, very little RAM is required to
store instruction
reduced instruction set computing. Small Instruction set where
RISC
each instruction is performed in one clock cycle.
very simple hardware/circuitry less silicon needed
each instruction is a single machine cycle therefore pipelining
Advantage of RISC
can be used to improve performance
lower energy consumption (can go into sleep mode)
compiler has to do more work to translate high-level code into
machine code
Disadvantage of RISC
more RAM is required to store the machine code instructions
RISC uses most computers used RISC
Program branch result The next instruction held in the PC is not carried out
Program branch reason Occurs due to an if statement function, procedure, call or loop
most microcontrollers and embedded systems like iPads and
CISC uses
iPhones use CISC
An extra processer used to supplement the functions of the
Co-Processor Systems primary processor.
It has a limited range of functions
Used as a specialized boost for the main processor to carry out
certain functions
Uses of Co-Processor systems
e.g. floating point arithmetic, graphic processing, digital signal
processing
Distribute workload across multiple CPU cores, thus achieving
Multi-Core systems
significantly higher performance
Parallel systems The capability to run multiple cores at the same time
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Science Computer Science Computer Architecture
Computer Science Paper 1
A register in the cpu that controls and coordinates the activities
Control Unit
of the cpu directing the flow of data
a series of connectors that transfer signals between internal
Bus
components
causes data from the addressed location in RAM to be placed on
Memory Read
the data bus
Causes data on the data bus to be written into the addressed
Memory Write
location.
Bus Request Indicates that a device is requesting the use of the data bus
Bus Grant Indicates that the CPU has granted access to the data bus.
System bus collective term for address, data and control bus
A bi-directional path for moving data and instructions between
Data bus
system components
Clock used to synchronize operations
A bi-directional bus to transmit command, timing and specific
Control bus
status information between system components
A one directional bus that transmits memory addresses that are
Address bus used as operands in programming instructions, so that data can
be retrieved from main memory
Arithmetic-Logic unit, preforms logical and arithmetic operations
on data
ALU
e.g. ADD, SUBTRACT, shift operations or Boolean logic
High speed memory cells, all arithmetic and logic happens in
Registers these, typically there are 16 general purpose registers in a CPU,
they are very fast
A special purpose register which stores the result of calculations
Accumulator
made by the ALU
https://quizlet.com/gb/300220496/computer-science-paper-1-flash-cards/ 1/37
,12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Holds the address of the next instruction to be executed, this can
Program Counter (PC) be the next instruction in a sequence of instructions, or a branch/
jump
Current instruction register (CIR) stores the actual instruction that is being decoded
stores the address of instructions and data that need to be
Memory address register (MAR)
fetched from or sent to memory
Memory data register (MDR) stores the data which is to be sent or fetched from memory
Interrupt registers generates and detects interrupts
PC
MAR
Address Bus
Memory
Data bus
Fetch Decode Execute register
MDR
sequence
CIR
Decode Unit
MAR
Address Bus
Main Memory
- Instructions pulled from memory and stored in main memory.
- Program Counter (a register) stores the address location of the
instruction
Fetch phase
- Program Counter and instructions are placed in the Instruction
Register (IR)
- Program Counter is incremented by 1
1. Instruction in CIR is decoded
2. Instruction is split into opcode and operand
3. the operand determines the type of instruction
Decode phase - if its the address of the data used with the operation it is copied
into the MAR
- if it the actual data to be operated on it is copied into the MDR
4. the data to be operated on is passed into the ALU/ acc
The appropriate instruction/ opcode is carried out on the data/
Execute phase
operand
- Clock speed
Main factors affecting
- Number of cores
preformance
- The amount and type of cache
The system clock generates a series of signals (1 or 0)
Clock speed synchronising with the CPU operations. The CPU cannot preform
faster than the system clock.
Positives of increasing clock You can carry out more instructions in a given time; improved
speed performance
What is clock speed measured Hz
in?
Negatives of increasing clock more heat generated meaning computers must be cooled (either
speed with heat sync/fan or water/oil cooling)
Positive of multiple cores may speed processing as concurrency is available
complicated circuitry (more expensive)
negatives of multiple cores
doesn't always improve performance
https://quizlet.com/gb/300220496/computer-science-paper-1-flash-cards/ 2/37
,12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Positives of increasing cache less time fetching data; improved performance
size
Negatives of increasing cache expensive, physically further from cpu and thus slower
size
Level 1 cache Small but extremely fast
Level 2 cache fairly fast and medium sized
Level 3 cache slower and bigger
When the computer architecture allows the next instruction to be
Pipelining fetched at the same time as the processor is preforming
arithmetic or logical operations. (buffer close to the processor)
The width of the address bus determines the maximum possible
capacity of the system
Bottleneck Address bus
e.g. is the address bus was 8 lines, the maximum it could transmit
would be 256
Bottleneck Data bus A wider bus can transmit larger values/ more bits per instruction
Instructions and data:
- Share memory
- Share bus system
Von Neumann architecture
- Stored in same format
- Same bit size for memory
- Single CPU and ALU
Instructions and data are:
- stored in separate memory units
Harvard architecture
- use separate bus systems
- allows for pipelining
Used extensively with embedded digital signal processing. The
Harvard architecture uses
two separate memories can have different characteristics
The general structure of the Von Neumann architecture used in
Von Neumann machine
most computers
Von Neumann:
- Used in conventional processors in PCs
- instructions and data share the same memory
- One bus
- Programs can be optimized in size
Comparison of Von Neumann
and Harvard architectures Harvard:
- Used in digital signal processing, embedded systems, mobile
communication
- Instructions and data held in separate memories
- Parallel data and instruction buses may be used
- Programs tend to be large
https://quizlet.com/gb/300220496/computer-science-paper-1-flash-cards/ 3/37
, 12/12/25, 12:08 PM Computer Science Paper 1 Flashcards | Quizlet
Modern high-performance CPU chips incorporate aspects of
both Von Neumann and Harvard architectures
Contemporary processor
architectures
e.g. memory for both data and instructions but cache is divided
into instruction and data and multiple parallel data buses
Complex instruction set computing, large number of instruction
CISC
each taking multiple machine cycles to carry out.
a single chip which contains 2 or more independent CPUs which
Chip Multi Processor
can execute independent instructions
Many specialized instructions had to be built into the hardware
even though about 20% will be used in the average program
more complex circuitry/hardware
Single machine instruction takes multiple machine cycles to carry
Disadvantage of CISC out
greater energy consumption
can't support pipelining
more silicon require to make
physically larger in size
compiler has to do very little work to translate high level
language to machine code
Advantage of CISC
because code is relatively short, very little RAM is required to
store instruction
reduced instruction set computing. Small Instruction set where
RISC
each instruction is performed in one clock cycle.
very simple hardware/circuitry less silicon needed
each instruction is a single machine cycle therefore pipelining
Advantage of RISC
can be used to improve performance
lower energy consumption (can go into sleep mode)
compiler has to do more work to translate high-level code into
machine code
Disadvantage of RISC
more RAM is required to store the machine code instructions
RISC uses most computers used RISC
Program branch result The next instruction held in the PC is not carried out
Program branch reason Occurs due to an if statement function, procedure, call or loop
most microcontrollers and embedded systems like iPads and
CISC uses
iPhones use CISC
An extra processer used to supplement the functions of the
Co-Processor Systems primary processor.
It has a limited range of functions
Used as a specialized boost for the main processor to carry out
certain functions
Uses of Co-Processor systems
e.g. floating point arithmetic, graphic processing, digital signal
processing
Distribute workload across multiple CPU cores, thus achieving
Multi-Core systems
significantly higher performance
Parallel systems The capability to run multiple cores at the same time
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