ELEC 3908 Fall 2023
LAB: III
MOSFET Square Law Parameter Execution
and SPICE Model Simulation
Submitted by:
Date Lab Performed: Friday 01 December 2023
Lab Section: A2
Carleton University
Ottawa, Ontario Canada
, Introduction
Analysing the silicon MOSFET’s ID vs VGS and ID vs VDS graphs is the aim of this lab
experiment in which these graphs was acquired from a silicon MOSFET which was measured
in the lab as well as use the experimental measurements to get the square law model’s critical
parameters. The MOSFET is an n-channel switching transistor that is derived from the
CD4007 DIP (Dual Inline Packaged) MOSFET, an integrated circuit [1]. IC-CAP software,
which has the ability to optimise a device’s simulation model, will be used to test the device.
In the data analysis phase that follows, the calculated findings and the experimental results
from IC-CAP will be compared.
Theory
In the introduction, the model used for the MOSFET parameter(s) extraction is the Square
Law Parameter Extraction model. This model consists of a set of equations which are
presented below:
Saturation drains source voltage:
V DS =V GS −V T equation (1) [1]
sat
From equation 1 above, VT is the threshold voltage measured in volts.
The current expression for VGS > VT and VDS < V DS in the Triode region is given as:
sat
2
W V DS
I D =μn Ĉox ( V GS−V T ) V DS− equation (2) [1]
L 2
μn = Surface Mobility of electrons
∈
Ĉ ox = 0 x = Oxide capacitance per unit area
t ox
In the saturation region, the current expression VGS > VT and VDS > VDssat
2
W ( V GS−V T )
I D =μn Ĉox
L ( 2 )
( 1+ λ V DS ) equation (3) [1]
From equation (3), λ represents the channel length modulation parameter ( V1 )
The threshold voltage is the sum of a “zero-bias” value plus a term depending on the source
substrate bias. Thus, the equation is as follows
V T =V ¿ −γ ( √ V SB +2 φF −√ 2 φ F ) equation (4) [1]
LAB: III
MOSFET Square Law Parameter Execution
and SPICE Model Simulation
Submitted by:
Date Lab Performed: Friday 01 December 2023
Lab Section: A2
Carleton University
Ottawa, Ontario Canada
, Introduction
Analysing the silicon MOSFET’s ID vs VGS and ID vs VDS graphs is the aim of this lab
experiment in which these graphs was acquired from a silicon MOSFET which was measured
in the lab as well as use the experimental measurements to get the square law model’s critical
parameters. The MOSFET is an n-channel switching transistor that is derived from the
CD4007 DIP (Dual Inline Packaged) MOSFET, an integrated circuit [1]. IC-CAP software,
which has the ability to optimise a device’s simulation model, will be used to test the device.
In the data analysis phase that follows, the calculated findings and the experimental results
from IC-CAP will be compared.
Theory
In the introduction, the model used for the MOSFET parameter(s) extraction is the Square
Law Parameter Extraction model. This model consists of a set of equations which are
presented below:
Saturation drains source voltage:
V DS =V GS −V T equation (1) [1]
sat
From equation 1 above, VT is the threshold voltage measured in volts.
The current expression for VGS > VT and VDS < V DS in the Triode region is given as:
sat
2
W V DS
I D =μn Ĉox ( V GS−V T ) V DS− equation (2) [1]
L 2
μn = Surface Mobility of electrons
∈
Ĉ ox = 0 x = Oxide capacitance per unit area
t ox
In the saturation region, the current expression VGS > VT and VDS > VDssat
2
W ( V GS−V T )
I D =μn Ĉox
L ( 2 )
( 1+ λ V DS ) equation (3) [1]
From equation (3), λ represents the channel length modulation parameter ( V1 )
The threshold voltage is the sum of a “zero-bias” value plus a term depending on the source
substrate bias. Thus, the equation is as follows
V T =V ¿ −γ ( √ V SB +2 φF −√ 2 φ F ) equation (4) [1]
