EEL 4712 Final Exam | Questions and Solutions | Fall 2025/26 Update | 100% Correct.

EEL 4712 - Digital Design M :
Exam 1 — Fall Semester 2025 Name f P/ L
1. VHDL specification
18 pts.| Given the following circuit diagram, specify (on the next page) the ARCHITECTURE for it in
VHDL.

Prob1Circuit
ParityChecker (PD)


l% :— D
LD | > PD
CLR o2

(serial) IN ShiftRegister (SR) /
Wi (70D
Z%/ ”
CLK >
L—— »Din Q31—
Q30 | )_‘_, z
SHF SHF s.
> Q0 ——


XOIR
e PDis a D flip-flop (and @R gate) with asynchronous CLR and synchronous LD. The CLR
signal has priority over LD. Otherwise, it “holds’.
* SR is a 32-bit shift register: If SHF = 1, it will synchronously shift right (Q31 <= IN) , else
“holds”.



Given below is the ENTITY specification, put your answer for the ARCHITECTURE section
on the next page.

LIBRARY |EEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Prob1Circuit IS
PORT(LD, CLR, IN, CLK, SHF : IN STD_LOGIC;
PD, Z: OUT STD_LOGIC);
END Prob1Circuit;

, EEL 4712 - Digital Design
Exam 1 - Fall Semester 2025 Name

1. (continued) Complete the following VHDL code to define the ARCHITECTURE section.
ARCHITECTURE behaviorArch OF Prob1Circuit
SIGNAL 7, P D STD-L06/C ¢
St L Q © STRLOBI VEeror (21 2w 3 P
BEGIN

PROCESS (£2K, (LK)



Alnd
BEGIN - PROCES 5


iy
JF LLR =11 THEW ' " .




\s
Ersir ' ( cLKIEVENT AP Lt =1 THEn ( A2




&
I L= THEN /éf ry D
FongtD < = IN KR %W -
EMD 1 F ) J

IF SHE = JTHEN
FOR 1N Q72 30 Loor
Fophe) <= tenglli+); | Sft ¢ &({A‘?—é‘?/


= T4/ ) g


ol = (THERS 7)) THE
W 2»4- VA /flfi
% ELfiE " flzfi{ V7%
== 24 Al
L2K OOT) g /7 5 /afifl//
PP <= /Idpfl/fifij /“

CEND PHOAESS |
END behaviorArch;