ECEN 350 Final Study questions & answers rated A+
updated
1. (True or False) The following .
is the complete RTL
description of the "AND" 8. The B instruction does not
instruction: require the registerfile at
R[rd] = R[rs] & R[rt]; all.
2. Adding two ports to an SRAM
means increasing each cell by
transistors. (how many?)
3. Fetch, and Execute are
the three phases of an
instructions life-cycle.
4. For all D-Type instructions,
Read Data 2 is connected to
the ALU.
5. Hardware that is not in use
for a given instruction (on
the unified hardware) is
removed until need- ed to
save power.
6. RTL defines the actions of
an in- struction in terms of
operations performed on
registers, with the outcome
being placed in another
register.
7. RTL stands for
,ECEN 350 Final Study questions & answers rated A+
updated
False
False
4
True
decode
register transfer language
False
True
,ECEN 350 Final Study questions & answers rated A+
updated
9. The fastest path through instruc- tions, the ALU is use
the log- ic determines its for effective
critical path and hence its calculation.
clock frequency.
15. The registerfile does not
10. The register file must have produce any output on Read
three ports (two read and Data 1 and Read Data 2 for
one write) in order to directly the B instruction.
support D-Type in- structions.
11. There are many different
possi- ble implementations
of a particu- lar ISA in
hardware.
12. are used to allow for
dif- ferent inputs to a given
piece of hardware when it
requires differ- ent inputs
when used by differ- ent
instructions. For example, it is
used on the input to the
register- file's Write Address
input to select between Rd and
Rt depending on which
instruction is executing.
13. For all R-Type instruction,
Read Data 2 is connected
to the ALU.
14. In the LDUR and STUR
,ECEN 350 Final Study questions & answers rated A+
updated
False
False
True
True
address
multiplexers
False
updated
1. (True or False) The following .
is the complete RTL
description of the "AND" 8. The B instruction does not
instruction: require the registerfile at
R[rd] = R[rs] & R[rt]; all.
2. Adding two ports to an SRAM
means increasing each cell by
transistors. (how many?)
3. Fetch, and Execute are
the three phases of an
instructions life-cycle.
4. For all D-Type instructions,
Read Data 2 is connected to
the ALU.
5. Hardware that is not in use
for a given instruction (on
the unified hardware) is
removed until need- ed to
save power.
6. RTL defines the actions of
an in- struction in terms of
operations performed on
registers, with the outcome
being placed in another
register.
7. RTL stands for
,ECEN 350 Final Study questions & answers rated A+
updated
False
False
4
True
decode
register transfer language
False
True
,ECEN 350 Final Study questions & answers rated A+
updated
9. The fastest path through instruc- tions, the ALU is use
the log- ic determines its for effective
critical path and hence its calculation.
clock frequency.
15. The registerfile does not
10. The register file must have produce any output on Read
three ports (two read and Data 1 and Read Data 2 for
one write) in order to directly the B instruction.
support D-Type in- structions.
11. There are many different
possi- ble implementations
of a particu- lar ISA in
hardware.
12. are used to allow for
dif- ferent inputs to a given
piece of hardware when it
requires differ- ent inputs
when used by differ- ent
instructions. For example, it is
used on the input to the
register- file's Write Address
input to select between Rd and
Rt depending on which
instruction is executing.
13. For all R-Type instruction,
Read Data 2 is connected
to the ALU.
14. In the LDUR and STUR
,ECEN 350 Final Study questions & answers rated A+
updated
False
False
True
True
address
multiplexers
False
