Solution Manual for Computer Organization and Architecture: Designing for Performance (11th Edition) by Stallings

TABLE OF CONTENTS




Chapter 1 Introduction ........................................................................................... 5
Chapter 2 Computer Evolution and Performance ............................................. 6
Chapter 3 Computer Function and Interconnection ........................................ 14
Chapter 4 Cache Memory .................................................................................... 19
Chapter 5 Internal Memory ................................................................................. 32
Chapter 6 External Memory ................................................................................ 38
Chapter 7 Input/Output ....................................................................................... 43
Chapter 8 Operating System Support ................................................................ 50
Chapter 9 Computer Arithmetic ......................................................................... 57
Chapter 10 Instruction Sets: Characteristics and Functions............................ 69
Chapter 11 Instruction Sets: Addressing Modes and Formats ....................... 80
Chapter 12 Processor Structure and Function .................................................. 85
Chapter 13 Reduced Instruction Set Computers .............................................. 92
Chapter 14 Instruction-Level Parallelism and Superscalar Processors ......... 97
Chapter 15 Control Unit Operation .................................................................. 103
Chapter 16 Microprogrammed Control ........................................................... 106
Chapter 17 Parallel Processing .......................................................................... 109
Chapter 18 Multicore Computers ..................................................................... 118
Chapter 19 Number Systems ............................................................................. 121
Chapter 20 Digital Logic .................................................................................... 122
Chapter 21 The IA-64 Architecture ................................................................... 126
Appendix B Assembly Language and Related Topics................................... 130




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, CHAPTER 1 INTRODUCTION


A NSWERS TO Q UESTIONS
1.1 Computer architecture refers to those attributes of a system visible to a
programmer or, put another way, those attributes that have a direct impact on the
logical execution of a program. Computer organization refers to the operational
units and their interconnections that realize the architectural specifications.
Examples of architectural attributes include the instruction set, the number of bits
used to represent various data types (e.g., numbers, characters), I/O mechanisms,
and techniques for addressing memory. Organizational attributes include those
hardware details transparent to the programmer, such as control signals;
interfaces between the computer and peripherals; and the memory technology
used.

1.2 Computer structure refers to the way in which the components of a computer are
interrelated. Computer function refers to the operation of each individual
component as part of the structure.

1.3 Data processing; data storage; data movement; and control.

1.4 Central processing unit (CPU): Controls the operation of the computer and
performs its data processing functions; often simply referred to as processor.
Main memory: Stores data.
I/O: Moves data between the computer and its external environment.
System interconnection: Some mechanism that provides for communication
among CPU, main memory, and I/O. A common example of system
interconnection is by means of a system bus, consisting of a number of conducting
wires to which all the other components attach.

1.5 Control unit: Controls the operation of the CPU and hence the computer
Arithmetic and logic unit (ALU): Performs the computer’s data processing
functions
Registers: Provides storage internal to the CPU
CPU interconnection: Some mechanism that provides for communication among
the control unit, ALU, and registers




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, CHAPTER 2 COMPUTER EVOLUTION AND
PERFORMANCE

A NSWERS TO Q UESTIONS
2.1 In a stored program computer, programs are represented in a form suitable for
storing in memory alongside the data. The computer gets its instructions by reading
them from memory, and a program can be set or altered by setting the values of a
portion of memory.

2.2 A main memory, which stores both data and instructions: an arithmetic and logic
unit (ALU) capable of operating on binary data; a control unit, which interprets
the instructions in memory and causes them to be executed; and input and output
(I/O) equipment operated by the control unit.

2.3 Gates, memory cells, and interconnections among gates and memory cells.

2.4 Moore observed that the number of transistors that could be put on a single chip
was doubling every year and correctly predicted that this pace would continue
into the near future.

2.5 Similar or identical instruction set: In many cases, the same set of machine
instructions is supported on all members of the family. Thus, a program that
executes on one machine will also execute on any other. Similar or identical
operating system: The same basic operating system is available for all family
members. Increasing speed: The rate of instruction execution increases in going
from lower to higher family members. Increasing Number of I/O ports: In going
from lower to higher family members. Increasing memory size: In going from
lower to higher family members. Increasing cost: In going from lower to higher
family members.

2.6 In a microprocessor, all of the components of the CPU are on a single chip.


A NSWERS TO P ROBLEMS
2.1 This program is developed in [HAYE98]. The vectors A, B, and C are each stored
in 1,000 contiguous locations in memory, beginning at locations 1001, 2001, and
3001, respectively. The program begins with the left half of location 3. A counting
variable N is set to 999 and decremented after each step until it reaches –1. Thus,
the vectors are processed from high location to low location.


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, Location Instruction Comments
0 999 Constant (count N)
1 1 Constant
2 1000 Constant
3L LOAD M(2000) Transfer A(I) to AC
3R ADD M(3000) Compute A(I) + B(I)
4L STOR M(4000) Transfer sum to C(I)
4R LOAD M(0) Load count N
5L SUB M(1) Decrement N by 1
5R JUMP+ M(6, 20:39) Test N and branch to 6R if nonnegative
6L JUMP M(6, 0:19) Halt
6R STOR M(0) Update N
7L ADD M(1) Increment AC by 1
7R ADD M(2)
8L STOR M(3, 8:19) Modify address in 3L
8R ADD M(2)
9L STOR M(3, 28:39) Modify address in 3R
9R ADD M(2)
10L STOR M(4, 8:19) Modify address in 4L
10R JUMP M(3, 0:19) Branch to 3L

2.2 a.
Opcode Operand
00000001 000000000010

b. First, the CPU must make access memory to fetch the instruction. The
instruction contains the address of the data we want to load. During the execute
phase accesses memory to load the data value located at that address for a total
of two trips to memory.

2.3 To read a value from memory, the CPU puts the address of the value it wants into
the MAR. The CPU then asserts the Read control line to memory and places the
address on the address bus. Memory places the contents of the memory location
passed on the data bus. This data is then transferred to the MBR. To write a value
to memory, the CPU puts the address of the value it wants to write into the MAR.
The CPU also places the data it wants to write into the MBR. The CPU then asserts
the Write control line to memory and places the address on the address bus and
the data on the data bus. Memory transfers the data on the data bus into the
corresponding memory location.




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