, THIRD EDITION
COMPUTER SYSTEM
ARCHITECTURE
PR
O
FD
M. Morris Mano
California State University
Los Angeles
O
C
,The author and publisher of this book have used their best efforts in preparing this book. These efforts include
the development, research, and testing of the theories to determine their effectiveness. The author and
publisher make no warranty of any kind, expressed or implied, with regard to these programs or the docu-
mentation contained in this book. The author and publisher shall not be liable in any event for incidental or
consequential damages in connection with, or arising out of the furnishing, performance, or use of these
theories and programs.
Authorized adaptation from the United States edition, entitled Computer System Architecture, Third Edition,
ISBN: 0131755633 by Mano, Morris M., published by Pearson Education, Inc., © 1993
PR
Indian Subcontinent Adaptation
Copyright © 2007 Dorling Kindersley (India) Pvt. Ltd.
This book is sold subject to the condition that it shall not, by way of trade or otherwise, be lent, resold, hired
out, or otherwise circulated without the publisher’s prior written consent in any form of binding or cover
other than that in which it is published and without a similar condition including this condition being
imposed on the subsequent purchaser and without limiting the rights under copyright reserved above, no
part of this publication may be reproduced, stored in or introduced into a retrieval system, or transmitted in
O
any form or by any means (electronic, mechanical, photocopying, recording or otherwise), without the prior
written permission of both the copyright owner and the above-mentioned publisher of this book.
No part of this eBook may be used or reproduced in any manner whatsoever without the publisher’s
FD
prior written consent.
This eBook may or may not include all assets that were part of the print version. The publisher
reserves the right to remove any material in this eBook at any time.
ISBN 81-317-0070-4
O
eISBN 978-93-325-7613-1
First Impression, 2007
C
This edition is manufactured in India and is authorized for sale only in India, Bangladesh, Bhutan, Pakistan,
Nepal, Sri Lanka and the Maldives.
Published by Dorling Kindersley (India) Pvt. Ltd., licensees of Pearson Education in South Asia.
Head Office: 15th Floor, Tower-B, World Trade Tower, Plot No. 1, Block-C, Sector-16,
Noida 201 301, Uttar Pradesh, India.
Registered Office: 4th Floor, Software Block, Elnet Software City, TS-140, Block 2 & 9,
Rajiv Gandhi Salai, Taramani, Chennai 600 113, Tamil Nadu, India.
Fax: 080-30461003, Phone: 080-30461060
www.pearson.co.in, Email:
, Contents
Preface xv
CHAPTER ONE
PR
Digital Logic Circuits 1
1-1 Digital Computers 1
1-2 Logic Gates 5
1-3 Boolean Algebra 7
Complement of a Function 12
O
1-4 Map Simplification 12
Product-of-Sums Simplification 16
Don’t-Care Conditions 18
FD
1-5 Combinational Circuits 20
Half-Adder 21
Full-Adder 22
1-6 Flip-Flops 24
SR Flip-Flop 24
D Flip-Flop 25
O
JK Flip-Flop 26
T Flip-Flop 26
Edge-Triggered Flip-Flops 27
Excitation Tables 28
C
1-7 Sequential Circuits 29
Flip-Flop Input Equations 30
State Table 31
State Diagram 33
Design Example 33
Design Procedure 36
Problems 38
References 40
iii
,iv Contents
CHAPTER TWO
Digital Components 41
2-1 Integrated Circuits 41
2-2 Decoders 43
NAND Gate Decoder 45
Decoder Expansion 46
Encoders 47
2-3 Multiplexers 47
2-4 Registers 50
Register with Parallel Load 50
2-5 Shift Registers 52
Bidirectional Shift Register with Parallel Load 53
2-6 Binary Counters 55
PR
Binary Counter with Parallel Load 56
2-7 Memory Unit 59
Random-Access Memory 60
Read-Only Memory 61
Types of ROMs 62
Problems 63
O
References 65
FD
CHAPTER THREE
Data Representation 67
3-1 Data Types 67
Number Systems 68
Octal and Hexadecimal Numbers 69
O
Decimal Representation 72
Alphanumeric Representation 73
3-2 Complements 74
(r ⫺ 1)’s Complement 75
C
(r’s) Complement 75
Subtraction of Unsigned Numbers 76
3-3 Fixed-Point Representation 77
Integer Representation 78
Arithmetic Addition 79
Arithmetic Subtraction 80
Overflow 80
Decimal Fixed-Point Representation 81
3-4 Floating-Point Representation 83
, Contents v
3-5 Other Binary Codes 84
Gray Code 85
Other Decimal Codes 85
Other Alphanumeric Codes 87
3-6 Error Detection Codes 87
Problems 90
References 91
CHAPTER FOUR
Register Transfer and Microoperations 93
4-1 Register Transfer Language 93
4-2 Register Transfer 95
PR
4-3 Bus and Memory Transfers 97
Three-State Bus Buffers 100
Memory Transfer 101
4-4 Arithmetic Microoperations 102
Binary Adder 103
Binary Adder-Subtractor 104
O
Binary Incrementer 105
Arithmetic Circuit 106
4-5 Logic Microoperations 108
List of Logic Microoperations 109
FD
Hardware Implementation 111
Some Applications 111
4-6 Shift Microoperations 114
Hardware Implementation 115
4-7 Arithmetic Logic Shift Unit 116
4-8 Hardware Description Languages 118
O
Introduction to VHDL 119
Basic Framework and Syntax 119
Problems 121
C
References 124
CHAPTER FIVE
Basic Computer Organization and Design 125
5-1 Instruction Codes 125
Stored Program Organization 127
Indirect Address 128
,vi Contents
5-2 Computer Registers 129
Common Bus System 131
5-3 Computer Instructions 134
Instruction Set Completeness 136
5-4 Timing and Control 137
5-5 Instruction Cycle 141
Fetch and Decode 141
Determine the Type of Instruction 143
Register-Reference Instructions 145
5-6 Memory-Reference Instructions 147
AND to AC 147
ADD to AC 148
LDA: Load to AC 148
STA: Store AC 149
BUN: Branch Unconditionally 149
PR
BSA: Branch and Save Return Address 149
ISZ: Increment and Skip if Zero 151
Control Flowchart 151
5-7 Input–Output and Interrupt 152
Input–Output Configuration 153
Input–Output Instructions 154
O
Program Interrupt 155
Interrupt Cycle 158
5-8 Complete Computer Description 159
5-9 Design of Basic Computer 159
FD
Control Logic Gates 160
Control of Registers and Memory 160
Control of Single Flip-flops 164
Control of Common Bus 164
5-10 Design of Accumulator Logic 166
Control of AC Register 167
O
Adder and Logic Circuit 168
Problems 169
References 173
C
CHAPTER SIX
Programming the Basic Computer 175
6-1 Introduction 175
6-2 Machine Language 176
, Contents vii
6-3 Assembly Language 181
Rules of the Language 181
An Example 183
Translation to Binary 184
6-4 The Assembler 185
Representation of Symbolic
Program in Memory 186
First Pass 187
Second Pass 189
6-5 Program Loops 192
6-6 Programming Arithmetic and Logic Operations 194
Multiplication Program 195
Double-Precision Addition 198
Logic Operations 199
Shift Operations 199
PR
6-7 Subroutines 200
Subroutine Parameters and
Data Linkage 202
6-8 Input–Output Programming 205
Character Manipulation 206
Program Interrupt 207
O
Problems 210
References 213
FD
CHAPTER SEVEN
Microprogrammed Control 215
7-1 Control Memory 215
O
7-2 Address Sequencing 218
Conditional Branching 219
Mapping of Instruction 221
C
Subroutines 222
7-3 Microprogram Example 222
Computer Configuration 222
Microinstruction Format 224
Symbolic Microinstructions 227
The Fetch Routine 228
Symbolic Microprogram 229
Binary Microprogram 231
,viii Contents
7-4 Design of Control Unit 233
Microprogram Sequencer 234
Problems 237
References 240
CHAPTER EIGHT
Central Processing Unit 243
8-1 Introduction 243
8-2 General Register Organization 244
Control Word 245
Examples of Microoperations 248
PR
8-3 Stack Organization 249
Register Stack 249
Memory Stack 251
Reverse Polish Notation 253
Evaluation of Arithmetic Expressions 255
8-4 Instruction Formats 257
O
Three-Address Instructions 260
Two-Address Instructions 260
One-Address Instructions 261
Zero-Address Instructions 261
FD
RISC Instructions 261
8-5 Addressing Modes 262
Numerical Example 266
8-6 Data Transfer and Manipulation 268
Data Transfer Instructions 269
Data Manipulation Instructions 270
O
Arithmetic Instructions 271
Logical and Bit Manipulation Instructions 272
Shift Instructions 273
C
8-7 Program Control 275
Status Bit Conditions 276
Conditional Branch Instructions 277
Subroutine Call and Return 280
Program Interrupt 281
Types of Interrupts 283
8-8 Reduced Instruction Set Computer (RISC) 284
CISC Characteristics 285
RISC Characteristics 286
, Contents ix
Overlapped Register Windows 287
Berkeley RISC I 290
Problems 293
References 299
CHAPTER NINE
Pipeline and Vector Processing 301
9-1 Parallel Processing 301
9-2 Pipelining 304
General Considerations 306
9-3 Arithmetic Pipeline 309
9-4 Instruction Pipeline 312
PR
Example: Four-Segment Instruction Pipeline 313
Data Dependency 315
Handling of Branch Instructions 316
9-5 RISC Pipeline 317
Example: Three-Segment Instruction Pipeline 318
Delayed Load 319
O
Delayed Branch 320
9-6 Vector Processing 321
Vector Operations 323
Matrix Multiplication 324
FD
Memory Interleaving 326
Superscalar Processors 327
Supercomputers 328
9-7 Array Processors 329
Attached Array Processor 329
SIMD Array Processor 330
O
Problems 331
References 333
C
CHAPTER TEN
Computer Arithmetic 335
10-1 Introduction 335
10-2 Addition and Subtraction 336
Addition and Subtraction with
Signed-Magnitude Data 337
COMPUTER SYSTEM
ARCHITECTURE
PR
O
FD
M. Morris Mano
California State University
Los Angeles
O
C
,The author and publisher of this book have used their best efforts in preparing this book. These efforts include
the development, research, and testing of the theories to determine their effectiveness. The author and
publisher make no warranty of any kind, expressed or implied, with regard to these programs or the docu-
mentation contained in this book. The author and publisher shall not be liable in any event for incidental or
consequential damages in connection with, or arising out of the furnishing, performance, or use of these
theories and programs.
Authorized adaptation from the United States edition, entitled Computer System Architecture, Third Edition,
ISBN: 0131755633 by Mano, Morris M., published by Pearson Education, Inc., © 1993
PR
Indian Subcontinent Adaptation
Copyright © 2007 Dorling Kindersley (India) Pvt. Ltd.
This book is sold subject to the condition that it shall not, by way of trade or otherwise, be lent, resold, hired
out, or otherwise circulated without the publisher’s prior written consent in any form of binding or cover
other than that in which it is published and without a similar condition including this condition being
imposed on the subsequent purchaser and without limiting the rights under copyright reserved above, no
part of this publication may be reproduced, stored in or introduced into a retrieval system, or transmitted in
O
any form or by any means (electronic, mechanical, photocopying, recording or otherwise), without the prior
written permission of both the copyright owner and the above-mentioned publisher of this book.
No part of this eBook may be used or reproduced in any manner whatsoever without the publisher’s
FD
prior written consent.
This eBook may or may not include all assets that were part of the print version. The publisher
reserves the right to remove any material in this eBook at any time.
ISBN 81-317-0070-4
O
eISBN 978-93-325-7613-1
First Impression, 2007
C
This edition is manufactured in India and is authorized for sale only in India, Bangladesh, Bhutan, Pakistan,
Nepal, Sri Lanka and the Maldives.
Published by Dorling Kindersley (India) Pvt. Ltd., licensees of Pearson Education in South Asia.
Head Office: 15th Floor, Tower-B, World Trade Tower, Plot No. 1, Block-C, Sector-16,
Noida 201 301, Uttar Pradesh, India.
Registered Office: 4th Floor, Software Block, Elnet Software City, TS-140, Block 2 & 9,
Rajiv Gandhi Salai, Taramani, Chennai 600 113, Tamil Nadu, India.
Fax: 080-30461003, Phone: 080-30461060
www.pearson.co.in, Email:
, Contents
Preface xv
CHAPTER ONE
PR
Digital Logic Circuits 1
1-1 Digital Computers 1
1-2 Logic Gates 5
1-3 Boolean Algebra 7
Complement of a Function 12
O
1-4 Map Simplification 12
Product-of-Sums Simplification 16
Don’t-Care Conditions 18
FD
1-5 Combinational Circuits 20
Half-Adder 21
Full-Adder 22
1-6 Flip-Flops 24
SR Flip-Flop 24
D Flip-Flop 25
O
JK Flip-Flop 26
T Flip-Flop 26
Edge-Triggered Flip-Flops 27
Excitation Tables 28
C
1-7 Sequential Circuits 29
Flip-Flop Input Equations 30
State Table 31
State Diagram 33
Design Example 33
Design Procedure 36
Problems 38
References 40
iii
,iv Contents
CHAPTER TWO
Digital Components 41
2-1 Integrated Circuits 41
2-2 Decoders 43
NAND Gate Decoder 45
Decoder Expansion 46
Encoders 47
2-3 Multiplexers 47
2-4 Registers 50
Register with Parallel Load 50
2-5 Shift Registers 52
Bidirectional Shift Register with Parallel Load 53
2-6 Binary Counters 55
PR
Binary Counter with Parallel Load 56
2-7 Memory Unit 59
Random-Access Memory 60
Read-Only Memory 61
Types of ROMs 62
Problems 63
O
References 65
FD
CHAPTER THREE
Data Representation 67
3-1 Data Types 67
Number Systems 68
Octal and Hexadecimal Numbers 69
O
Decimal Representation 72
Alphanumeric Representation 73
3-2 Complements 74
(r ⫺ 1)’s Complement 75
C
(r’s) Complement 75
Subtraction of Unsigned Numbers 76
3-3 Fixed-Point Representation 77
Integer Representation 78
Arithmetic Addition 79
Arithmetic Subtraction 80
Overflow 80
Decimal Fixed-Point Representation 81
3-4 Floating-Point Representation 83
, Contents v
3-5 Other Binary Codes 84
Gray Code 85
Other Decimal Codes 85
Other Alphanumeric Codes 87
3-6 Error Detection Codes 87
Problems 90
References 91
CHAPTER FOUR
Register Transfer and Microoperations 93
4-1 Register Transfer Language 93
4-2 Register Transfer 95
PR
4-3 Bus and Memory Transfers 97
Three-State Bus Buffers 100
Memory Transfer 101
4-4 Arithmetic Microoperations 102
Binary Adder 103
Binary Adder-Subtractor 104
O
Binary Incrementer 105
Arithmetic Circuit 106
4-5 Logic Microoperations 108
List of Logic Microoperations 109
FD
Hardware Implementation 111
Some Applications 111
4-6 Shift Microoperations 114
Hardware Implementation 115
4-7 Arithmetic Logic Shift Unit 116
4-8 Hardware Description Languages 118
O
Introduction to VHDL 119
Basic Framework and Syntax 119
Problems 121
C
References 124
CHAPTER FIVE
Basic Computer Organization and Design 125
5-1 Instruction Codes 125
Stored Program Organization 127
Indirect Address 128
,vi Contents
5-2 Computer Registers 129
Common Bus System 131
5-3 Computer Instructions 134
Instruction Set Completeness 136
5-4 Timing and Control 137
5-5 Instruction Cycle 141
Fetch and Decode 141
Determine the Type of Instruction 143
Register-Reference Instructions 145
5-6 Memory-Reference Instructions 147
AND to AC 147
ADD to AC 148
LDA: Load to AC 148
STA: Store AC 149
BUN: Branch Unconditionally 149
PR
BSA: Branch and Save Return Address 149
ISZ: Increment and Skip if Zero 151
Control Flowchart 151
5-7 Input–Output and Interrupt 152
Input–Output Configuration 153
Input–Output Instructions 154
O
Program Interrupt 155
Interrupt Cycle 158
5-8 Complete Computer Description 159
5-9 Design of Basic Computer 159
FD
Control Logic Gates 160
Control of Registers and Memory 160
Control of Single Flip-flops 164
Control of Common Bus 164
5-10 Design of Accumulator Logic 166
Control of AC Register 167
O
Adder and Logic Circuit 168
Problems 169
References 173
C
CHAPTER SIX
Programming the Basic Computer 175
6-1 Introduction 175
6-2 Machine Language 176
, Contents vii
6-3 Assembly Language 181
Rules of the Language 181
An Example 183
Translation to Binary 184
6-4 The Assembler 185
Representation of Symbolic
Program in Memory 186
First Pass 187
Second Pass 189
6-5 Program Loops 192
6-6 Programming Arithmetic and Logic Operations 194
Multiplication Program 195
Double-Precision Addition 198
Logic Operations 199
Shift Operations 199
PR
6-7 Subroutines 200
Subroutine Parameters and
Data Linkage 202
6-8 Input–Output Programming 205
Character Manipulation 206
Program Interrupt 207
O
Problems 210
References 213
FD
CHAPTER SEVEN
Microprogrammed Control 215
7-1 Control Memory 215
O
7-2 Address Sequencing 218
Conditional Branching 219
Mapping of Instruction 221
C
Subroutines 222
7-3 Microprogram Example 222
Computer Configuration 222
Microinstruction Format 224
Symbolic Microinstructions 227
The Fetch Routine 228
Symbolic Microprogram 229
Binary Microprogram 231
,viii Contents
7-4 Design of Control Unit 233
Microprogram Sequencer 234
Problems 237
References 240
CHAPTER EIGHT
Central Processing Unit 243
8-1 Introduction 243
8-2 General Register Organization 244
Control Word 245
Examples of Microoperations 248
PR
8-3 Stack Organization 249
Register Stack 249
Memory Stack 251
Reverse Polish Notation 253
Evaluation of Arithmetic Expressions 255
8-4 Instruction Formats 257
O
Three-Address Instructions 260
Two-Address Instructions 260
One-Address Instructions 261
Zero-Address Instructions 261
FD
RISC Instructions 261
8-5 Addressing Modes 262
Numerical Example 266
8-6 Data Transfer and Manipulation 268
Data Transfer Instructions 269
Data Manipulation Instructions 270
O
Arithmetic Instructions 271
Logical and Bit Manipulation Instructions 272
Shift Instructions 273
C
8-7 Program Control 275
Status Bit Conditions 276
Conditional Branch Instructions 277
Subroutine Call and Return 280
Program Interrupt 281
Types of Interrupts 283
8-8 Reduced Instruction Set Computer (RISC) 284
CISC Characteristics 285
RISC Characteristics 286
, Contents ix
Overlapped Register Windows 287
Berkeley RISC I 290
Problems 293
References 299
CHAPTER NINE
Pipeline and Vector Processing 301
9-1 Parallel Processing 301
9-2 Pipelining 304
General Considerations 306
9-3 Arithmetic Pipeline 309
9-4 Instruction Pipeline 312
PR
Example: Four-Segment Instruction Pipeline 313
Data Dependency 315
Handling of Branch Instructions 316
9-5 RISC Pipeline 317
Example: Three-Segment Instruction Pipeline 318
Delayed Load 319
O
Delayed Branch 320
9-6 Vector Processing 321
Vector Operations 323
Matrix Multiplication 324
FD
Memory Interleaving 326
Superscalar Processors 327
Supercomputers 328
9-7 Array Processors 329
Attached Array Processor 329
SIMD Array Processor 330
O
Problems 331
References 333
C
CHAPTER TEN
Computer Arithmetic 335
10-1 Introduction 335
10-2 Addition and Subtraction 336
Addition and Subtraction with
Signed-Magnitude Data 337
