.CSE 490/590 – Midterm Exam –2025 V1 Solution
[Question 1] (10 Points)
Assume the presence of the following memories in a MIPS system:
i. L1 cache
ii. Main Memory
iii. L3 cache
iv. Registers
v. SSDs
vi. L2 cache
vii. Hard drive
Show the memory hierarchy and order them in terms of (State Increasing or decreasing order):
a. Speed
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSDs -> Hard Drive (decreasing)
b. Cost per byte
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSD -> Hard Drive (decreasing)
a. Memory capacity (Size)
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSD -> Hard Drive (increasing)
[Question 2] (10 Points)
a) Consider a direct-mapped cache of size 4 bytes. Each index in the cache can hold only 1
word (here 1 word = 1 byte). Fill in the missing cache blocks at each step according to
the address reference and specify whether it is a hit or a miss. The initial state of the
cache is provided. Address references are (in order):
Reference: 0x4 0x6 0xB 0x6
Tag Cache Tag Cache Tag Cache Tag Cache Tag Cache
Content Content Content Content Content
10b Mem(0x8) 01b M(0x4) 01b M(0x4) 01b M(0x4) 11b M(0xC)
01b Mem(0x5) 01b M(0x5) 01b M(0x5) 01b M(0x5) 01b M(0x5)
10b Mem(0xA 10b M(0xA) 01b M(0x6) 01b M(0x6) 01b M(0x6)
)
11b Mem(0xF) 11b M(0xF) 11b M(0xF) 10b M(0xB) 10b M(0xB)
hit / miss hit / miss hit / miss hit / miss
b) Calculate the hit rate for part a.
, March 12, 2025 CSE 490/590 Spring 2025 Midterm Exam Duration: 40 min
Hit rate = No. of hits / total requests = 1/4 = 0.25
[Question 3] (12 Points)
Consider three different processors P1, P2, and P3 executing the same instruction set.
Processor Clock Speed in GHz CPI
P1 1.5 2.5
P2 3.0 1.5
P3 4.0 2.5
Which processor has the highest performance expressed in instructions per second?
(1 GHz = 109 Hz). Show your work.
IPS = Cycles per second/CPI
P1: 1.5/2.5 = 0.6
P2: 3/1.5 = 2
P3: 4/2.5 = 1.6
P2 has the highest performance
[Question 4] (12 Points)
In the following instruction sequence, find all hazards. Rename the registers to eliminate the
anti-dependencies and output dependences. Assume you have FP registers up to $F16 available.
Show your work.
div.s F0, F2, F4
mult.s F4, F0, F6
add.s F0, F2, F12
sub.s F8, F14, F2
Potential hazards
RAW: F0 -> div.s and mult.s;
WAR: F4 -> div.s and mult.s, F0 -> mult.s and add.s
WAW: F0 -> div.s and add.s
div.s F0, F2, F4
mult.s F9, F0, F6
add.s F10, F2, F12
sub.s F8, F14, F2
[Question 1] (10 Points)
Assume the presence of the following memories in a MIPS system:
i. L1 cache
ii. Main Memory
iii. L3 cache
iv. Registers
v. SSDs
vi. L2 cache
vii. Hard drive
Show the memory hierarchy and order them in terms of (State Increasing or decreasing order):
a. Speed
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSDs -> Hard Drive (decreasing)
b. Cost per byte
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSD -> Hard Drive (decreasing)
a. Memory capacity (Size)
Registers -> L1 -> L2 -> L3 -> Main Memory -> SSD -> Hard Drive (increasing)
[Question 2] (10 Points)
a) Consider a direct-mapped cache of size 4 bytes. Each index in the cache can hold only 1
word (here 1 word = 1 byte). Fill in the missing cache blocks at each step according to
the address reference and specify whether it is a hit or a miss. The initial state of the
cache is provided. Address references are (in order):
Reference: 0x4 0x6 0xB 0x6
Tag Cache Tag Cache Tag Cache Tag Cache Tag Cache
Content Content Content Content Content
10b Mem(0x8) 01b M(0x4) 01b M(0x4) 01b M(0x4) 11b M(0xC)
01b Mem(0x5) 01b M(0x5) 01b M(0x5) 01b M(0x5) 01b M(0x5)
10b Mem(0xA 10b M(0xA) 01b M(0x6) 01b M(0x6) 01b M(0x6)
)
11b Mem(0xF) 11b M(0xF) 11b M(0xF) 10b M(0xB) 10b M(0xB)
hit / miss hit / miss hit / miss hit / miss
b) Calculate the hit rate for part a.
, March 12, 2025 CSE 490/590 Spring 2025 Midterm Exam Duration: 40 min
Hit rate = No. of hits / total requests = 1/4 = 0.25
[Question 3] (12 Points)
Consider three different processors P1, P2, and P3 executing the same instruction set.
Processor Clock Speed in GHz CPI
P1 1.5 2.5
P2 3.0 1.5
P3 4.0 2.5
Which processor has the highest performance expressed in instructions per second?
(1 GHz = 109 Hz). Show your work.
IPS = Cycles per second/CPI
P1: 1.5/2.5 = 0.6
P2: 3/1.5 = 2
P3: 4/2.5 = 1.6
P2 has the highest performance
[Question 4] (12 Points)
In the following instruction sequence, find all hazards. Rename the registers to eliminate the
anti-dependencies and output dependences. Assume you have FP registers up to $F16 available.
Show your work.
div.s F0, F2, F4
mult.s F4, F0, F6
add.s F0, F2, F12
sub.s F8, F14, F2
Potential hazards
RAW: F0 -> div.s and mult.s;
WAR: F4 -> div.s and mult.s, F0 -> mult.s and add.s
WAW: F0 -> div.s and add.s
div.s F0, F2, F4
mult.s F9, F0, F6
add.s F10, F2, F12
sub.s F8, F14, F2
