L
Sequential Circ. out
dep of current input & current state
Moore
After 2 correct
for I cell
-
: buttons unlock
.
current state collection
of all previous inputs
-
Bl = 0
A Password : Bl 13 " possible
inputs
ClaK Pulses
,
lockedBe alea
B1-00
·
latch (level trig) =
present state updated when clok has 0= 0
B2 -
01
133-10
a certain value B4-1
↑ (B3
FF Ledge trig)
= 1
when clak has
unlocked
present state updated after
·
value
-
. *
O= 1
.
certain transition Next State next dak
a
- -
SetupTime-time for
Present 0020
before
State
cck
edge that must be stable
po
-
Bl
signal Q, Qo ↑ Q QQQ Outpu
correct operation type
for
O
Hold Time-time after dcK edge that
signal must be stable
no
coret. O 01000000 8
I carct. 0 0 0 O
0 0 G 0 O
correct operation
2 corct 1 0 I
00000000
.
Sync Inputs transferred to output & clck edge
.
-
values
11
unused 0000000 0 g
Async Inputs values
transferred to output directly starts when2 correct
Realizatio
-
.
over
Specification typically state diagram -
a
force to start state (locked
State
Assig Assign of binary #S to the states QQFO
-
. - -
FF Inputs Eg Determ
. . .
-
dev .
from state transition table wh state assign. Exisc(0 2) :B +A ,
000 0
Optimization
-
are there similar states&
diff of
places transition table ? PLAsije =
#inputs
*
#prod terms outputs
.
OI 000
Mealy (state inputs) outputs func of
a
+
are a state
a inputs from 1-map of terms 1100 8
-
comes min
(state)
Moore outputs func of state
only buffer inverter AND Gates 10000
-
are a
gates
Q* =
Max Call freg for ffs
-
it's sum of the setup & max of Chold/prop) Small Scale
OR Gates
.QOFF
Integrated <10
gates
.
000
00
Prop.
delay time after cl
edge until output stabilizes MSI 10-100
-
gates Single
%
in
LSI
100 - few 1000 package
·
SR Latch VLSI several 1000 100s
of millions
-
Setup/ha
+ Ins
pHL
=
+phH = 4nS
I Gns
Metastable (violate
changeto se
Input
dea
&eff in series to pass
so Vye Logic/ Signalsbl
a
logico
Ai
I
Master Slaveff .
XOR
Sequential Design / D-ff .
s Present
=
S State Next State
A BC ** B* c*
·
*
S
&
·
-
D Yatch En D Q
I
change
· No
0 X No
***
10 Q = 0
c -
DQ -
A
11 Q = 1
PLA us ROM ·
: Designconsequen
De
Fit
D
decoding of ↑
000 010, 101 110 111 000
vor 2 not
.
gen , , , ,
like above but State tabl
tal Design o 5 1
- I
800
-
D
101
ABC A BGAA
↑
JBKB Jck
Suff
110 I I I
~
%
I X 0x0X
Har to hold input Low
after pur ?
↓
↳
X0Yy0x
on
11 X0 1 X
X
* x8
X I
JKQ*** Va
I 00 O & OX X0
969 *** **** **
Excitation
r
Bipolar-current slope defined by T-RC
CMOS-voltage
74ALS how many inputs can H= EABc(1 2 , 4,
,
7)
input IOMA H be driven
before ↑
output
100MAL
112mA
we
much
consume
current
too
Kmap HMS- -
4
=
Fanout =+driving diffamiymemba patible
3 state Var to address 8 positions need
23 =
8 - 3 terms A
3b
O inputs
Sequential Circ. out
dep of current input & current state
Moore
After 2 correct
for I cell
-
: buttons unlock
.
current state collection
of all previous inputs
-
Bl = 0
A Password : Bl 13 " possible
inputs
ClaK Pulses
,
lockedBe alea
B1-00
·
latch (level trig) =
present state updated when clok has 0= 0
B2 -
01
133-10
a certain value B4-1
↑ (B3
FF Ledge trig)
= 1
when clak has
unlocked
present state updated after
·
value
-
. *
O= 1
.
certain transition Next State next dak
a
- -
SetupTime-time for
Present 0020
before
State
cck
edge that must be stable
po
-
Bl
signal Q, Qo ↑ Q QQQ Outpu
correct operation type
for
O
Hold Time-time after dcK edge that
signal must be stable
no
coret. O 01000000 8
I carct. 0 0 0 O
0 0 G 0 O
correct operation
2 corct 1 0 I
00000000
.
Sync Inputs transferred to output & clck edge
.
-
values
11
unused 0000000 0 g
Async Inputs values
transferred to output directly starts when2 correct
Realizatio
-
.
over
Specification typically state diagram -
a
force to start state (locked
State
Assig Assign of binary #S to the states QQFO
-
. - -
FF Inputs Eg Determ
. . .
-
dev .
from state transition table wh state assign. Exisc(0 2) :B +A ,
000 0
Optimization
-
are there similar states&
diff of
places transition table ? PLAsije =
#inputs
*
#prod terms outputs
.
OI 000
Mealy (state inputs) outputs func of
a
+
are a state
a inputs from 1-map of terms 1100 8
-
comes min
(state)
Moore outputs func of state
only buffer inverter AND Gates 10000
-
are a
gates
Q* =
Max Call freg for ffs
-
it's sum of the setup & max of Chold/prop) Small Scale
OR Gates
.QOFF
Integrated <10
gates
.
000
00
Prop.
delay time after cl
edge until output stabilizes MSI 10-100
-
gates Single
%
in
LSI
100 - few 1000 package
·
SR Latch VLSI several 1000 100s
of millions
-
Setup/ha
+ Ins
pHL
=
+phH = 4nS
I Gns
Metastable (violate
changeto se
Input
dea
&eff in series to pass
so Vye Logic/ Signalsbl
a
logico
Ai
I
Master Slaveff .
XOR
Sequential Design / D-ff .
s Present
=
S State Next State
A BC ** B* c*
·
*
S
&
·
-
D Yatch En D Q
I
change
· No
0 X No
***
10 Q = 0
c -
DQ -
A
11 Q = 1
PLA us ROM ·
: Designconsequen
De
Fit
D
decoding of ↑
000 010, 101 110 111 000
vor 2 not
.
gen , , , ,
like above but State tabl
tal Design o 5 1
- I
800
-
D
101
ABC A BGAA
↑
JBKB Jck
Suff
110 I I I
~
%
I X 0x0X
Har to hold input Low
after pur ?
↓
↳
X0Yy0x
on
11 X0 1 X
X
* x8
X I
JKQ*** Va
I 00 O & OX X0
969 *** **** **
Excitation
r
Bipolar-current slope defined by T-RC
CMOS-voltage
74ALS how many inputs can H= EABc(1 2 , 4,
,
7)
input IOMA H be driven
before ↑
output
100MAL
112mA
we
much
consume
current
too
Kmap HMS- -
4
=
Fanout =+driving diffamiymemba patible
3 state Var to address 8 positions need
23 =
8 - 3 terms A
3b
O inputs
