CDA 3101
Introduction to Computer Organization
4.0 Credits
Final Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions (10 Questions)
1. Question:
In a typical CPU, the component responsible for fetching,
decoding, and executing instructions is known as the:
A. Arithmetic Logic Unit (ALU)
B. Control Unit
C. Register File
D. Cache Controller
Correct ANS: B. Control Unit
Rationale:
The Control Unit orchestrates the operations within the CPU by
issuing control signals that govern the execution of instructions
through the fetch‑decode‑execute cycle.
2. Question:
Which design feature in modern processors aims to increase
instruction throughput by overlapping the execution phases of
multiple instructions?
A. Superscalar execution
B. Pipelining
C. Multithreading
D. Out‑of‑order execution
Correct ANS: B. Pipelining
Rationale:
Pipelining divides instruction execution into stages so that several
instructions can be processed concurrently—each at a different
stage—thereby increasing throughput.
3. Question:
The addressing mode where the effective memory address is
obtained by adding a constant displacement to the contents of a
base register is called:
A. Immediate addressing
B. Direct addressing
©2025
, C. Base-plus-displacement addressing
D. Indexed addressing
Correct ANS: C. Base-plus-displacement addressing
Rationale:
In base-plus-displacement addressing, the effective address is
computed by summing a value in a base register with a fixed offset,
a common mode in many ISAs.
4. Question:
Which architectural style is characterized by a load/store design
in which only specific instructions access the memory?
A. Complex Instruction Set Computer (CISC)
B. Reduced Instruction Set Computer (RISC)
C. Very Long Instruction Word (VLIW)
D. Digital Signal Processor (DSP)
Correct ANS: B. Reduced Instruction Set Computer (RISC)
Rationale:
RISC architectures use a load/store model that separates data
movement from computation, thus simplifying the instruction set
and often enabling faster execution.
5. Question:
Dynamic branch prediction in pipelined processors is used to
reduce stalls. Which prediction mechanism commonly uses a 2‑bit
saturating counter?
A. Static branch prediction
B. Two-bit predictor
C. Global history prediction
D. Tournament predictor
Correct ANS: B. Two-bit predictor
Rationale:
A 2‑bit saturating counter allows a branch predictor to tolerate
minor fluctuations in branch behavior, thereby improving prediction
accuracy and reducing pipeline stalls.
©2025
Introduction to Computer Organization
4.0 Credits
Final Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions (10 Questions)
1. Question:
In a typical CPU, the component responsible for fetching,
decoding, and executing instructions is known as the:
A. Arithmetic Logic Unit (ALU)
B. Control Unit
C. Register File
D. Cache Controller
Correct ANS: B. Control Unit
Rationale:
The Control Unit orchestrates the operations within the CPU by
issuing control signals that govern the execution of instructions
through the fetch‑decode‑execute cycle.
2. Question:
Which design feature in modern processors aims to increase
instruction throughput by overlapping the execution phases of
multiple instructions?
A. Superscalar execution
B. Pipelining
C. Multithreading
D. Out‑of‑order execution
Correct ANS: B. Pipelining
Rationale:
Pipelining divides instruction execution into stages so that several
instructions can be processed concurrently—each at a different
stage—thereby increasing throughput.
3. Question:
The addressing mode where the effective memory address is
obtained by adding a constant displacement to the contents of a
base register is called:
A. Immediate addressing
B. Direct addressing
©2025
, C. Base-plus-displacement addressing
D. Indexed addressing
Correct ANS: C. Base-plus-displacement addressing
Rationale:
In base-plus-displacement addressing, the effective address is
computed by summing a value in a base register with a fixed offset,
a common mode in many ISAs.
4. Question:
Which architectural style is characterized by a load/store design
in which only specific instructions access the memory?
A. Complex Instruction Set Computer (CISC)
B. Reduced Instruction Set Computer (RISC)
C. Very Long Instruction Word (VLIW)
D. Digital Signal Processor (DSP)
Correct ANS: B. Reduced Instruction Set Computer (RISC)
Rationale:
RISC architectures use a load/store model that separates data
movement from computation, thus simplifying the instruction set
and often enabling faster execution.
5. Question:
Dynamic branch prediction in pipelined processors is used to
reduce stalls. Which prediction mechanism commonly uses a 2‑bit
saturating counter?
A. Static branch prediction
B. Two-bit predictor
C. Global history prediction
D. Tournament predictor
Correct ANS: B. Two-bit predictor
Rationale:
A 2‑bit saturating counter allows a branch predictor to tolerate
minor fluctuations in branch behavior, thereby improving prediction
accuracy and reducing pipeline stalls.
©2025
