CSE 230 Makeup Exam 3 Questions And Answers
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Assume that the cache miss rate for instruction fetch is 4% and the cache miss rate for data fetch/access is 3%.
Assume that a processor has a CPI of 2.5 without any memory stalls and the miss penalty is 260 clock cycles
for each miss.
Also assume that the frequency of all loads and stores in a program is 10%.
a). Assume that I is the instruction account (# of instructions). Compute the total number of memory-stall
cycles.
b). Compute the effective CPI with this cache and its miss rate.
c). Determine how much faster a processor would run with a perfect cache that never misses. i.e., Compute the
ratio of the CPU execution time = CPU_stall / CPI_no_stall
(CPU_stall is the answer from the part b.) ANS a) The total number of memory-stall cycles: 11.18 * I
cycles
b) Effective CPI: 13.68
c) The ratio of the CPU execution time (round to 3 digits after the decimal point): 5.472
L1 Cache is a cache for ___________ ANS cache
L2 Cache is a cache for ____________ ANS main memory
Main memory is a cache for _______________ ANS disks
TLB is a cache for _________________ ANS page table entries
Assume that main memory access take 65 ns and L1 caches are attached to the processor P1.
, a). For the processor P1, L1 miss rate is 10% and L1 hit time is 0.80 ns.
Compute its AMAT (average memory access time).
b). Now we will consider the addition of an L2 cache to the processor P1. Use the L1 cache capacities and hit
time from the part a) when solving the following problem. The L2 miss rate indicated is its local miss rate.
For the processor P1, L2 miss rate is 65% and L2 hit time is 16 ns.
Compute its AMAT. ANS a) AMAT = 7.3 ns
b) AMAT = 6.625 ns
Write-back ANS It updates values only to the block in the cache, then writing the modified block to the
memory when the block is replaced.
Reference bit ANS Tracks whether a page/block has been accessed and is used to implement a block/page
replacement scheme
Dirty Bit ANS It tracks whether a page/block has been written/changed since it was read into the
Memory/cache.
Page Fault ANS Virtual memory miss
Write-through ANS It updates both the cache and memory, ensuring that data is always consistent between
the two.
Write Buffer ANS A queue that holds data while the data is waiting to be written to memory.
Assume that you have a direct-mapped cache with 16 indices and each block can contain 16 words. Assuming
that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions:
a). How many bits in each address are used for its tag?
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Assume that the cache miss rate for instruction fetch is 4% and the cache miss rate for data fetch/access is 3%.
Assume that a processor has a CPI of 2.5 without any memory stalls and the miss penalty is 260 clock cycles
for each miss.
Also assume that the frequency of all loads and stores in a program is 10%.
a). Assume that I is the instruction account (# of instructions). Compute the total number of memory-stall
cycles.
b). Compute the effective CPI with this cache and its miss rate.
c). Determine how much faster a processor would run with a perfect cache that never misses. i.e., Compute the
ratio of the CPU execution time = CPU_stall / CPI_no_stall
(CPU_stall is the answer from the part b.) ANS a) The total number of memory-stall cycles: 11.18 * I
cycles
b) Effective CPI: 13.68
c) The ratio of the CPU execution time (round to 3 digits after the decimal point): 5.472
L1 Cache is a cache for ___________ ANS cache
L2 Cache is a cache for ____________ ANS main memory
Main memory is a cache for _______________ ANS disks
TLB is a cache for _________________ ANS page table entries
Assume that main memory access take 65 ns and L1 caches are attached to the processor P1.
, a). For the processor P1, L1 miss rate is 10% and L1 hit time is 0.80 ns.
Compute its AMAT (average memory access time).
b). Now we will consider the addition of an L2 cache to the processor P1. Use the L1 cache capacities and hit
time from the part a) when solving the following problem. The L2 miss rate indicated is its local miss rate.
For the processor P1, L2 miss rate is 65% and L2 hit time is 16 ns.
Compute its AMAT. ANS a) AMAT = 7.3 ns
b) AMAT = 6.625 ns
Write-back ANS It updates values only to the block in the cache, then writing the modified block to the
memory when the block is replaced.
Reference bit ANS Tracks whether a page/block has been accessed and is used to implement a block/page
replacement scheme
Dirty Bit ANS It tracks whether a page/block has been written/changed since it was read into the
Memory/cache.
Page Fault ANS Virtual memory miss
Write-through ANS It updates both the cache and memory, ensuring that data is always consistent between
the two.
Write Buffer ANS A queue that holds data while the data is waiting to be written to memory.
Assume that you have a direct-mapped cache with 16 indices and each block can contain 16 words. Assuming
that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions:
a). How many bits in each address are used for its tag?
