CS219 Computer Architecture I
Midterm Exam Review (Qns & Ans)
2025
Multiple Choice Questions
1. Which architecture type is designed to execute a single
instruction on multiple data elements?
o A) SISD
o B) SIMD
o C) MISD
o D) MIMD Answer: B) SIMD Rationale: SIMD (Single
Instruction, Multiple Data) allows a single instruction to
operate on multiple data points simultaneously,
enhancing performance in data parallelism.
2. In which stage of the instruction pipeline does the
instruction fetch occur?
o A) Decode
o B) Execute
o C) Fetch
o D) Write-back Answer: C)
Fetch Rationale: Instruction fetch is the initial stage in
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, the instruction pipeline, where the processor retrieves an
instruction from memory.
3. What is the primary purpose of cache memory in
computer architecture?
o A) To store the operating system
o B) To speed up data access for the CPU
o C) To reduce power consumption
o D) To increase data storage capacity Answer: B) To
speed up data access for the CPU Rationale: Cache
memory provides faster data access to the CPU by
storing frequently accessed data and instructions.
4. Which of the following is a common measure of processor
performance?
o A) CPU clock speed
o B) Instruction per cycle (IPC)
o C) FLOPS
o D) All of the above Answer: D) All of the
above Rationale: Each of these measures provides
insights into processor performance from different
perspectives, such as speed, efficiency, and throughput.
5. Which of the following architectures utilizes a single bus
to connect all components?
o A) Harvard Architecture
o B) Von Neumann Architecture
o C) RISC Architecture
o D) CISC Architecture Answer: B) Von Neumann
Architecture Rationale: The Von Neumann architecture
uses a single bus for both data and instructions, which
can lead to bottlenecks.
Fill-in-the-Blank Questions
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, 6. The process of breaking down a task into smaller sub-
tasks is known as __________. Answer: Task
Decomposition Rationale: Task decomposition is essential
in parallel computing to enhance efficiency and workload
distribution.
7. The __________ describes the method of accessing
memory either as single or multiple data items in one
operation. Answer: Memory Access Mode Rationale:
Different memory access modes can significantly impact
performance during data retrieval and processing.
8. In pipelined processors, a ________ occurs when an
instruction depends on the result of a previous
instruction. Answer: Data Hazard Rationale: Data hazards
can stall the pipeline, leading to inefficiencies in instruction
processing.
9. The principle of __________ states that no single
instruction affects the execution speed of other
instructions. Answer: Instruction-Level Parallelism
Rationale: Instruction-level parallelism enables multiple
instructions to be executed simultaneously without
interference.
10. The main advantage of using
__________ architecture is the separation of data and
instruction memory. Answer: Harvard Rationale: Harvard
architecture helps in decreasing the bottleneck associated
with the shared bus seen in Von Neumann architecture.
True/False Questions
11. T/F: Parallel computing aims
solely to enhance processing speed. Answer: False
Rationale: While speed is a significant goal, parallel
©2025
Midterm Exam Review (Qns & Ans)
2025
Multiple Choice Questions
1. Which architecture type is designed to execute a single
instruction on multiple data elements?
o A) SISD
o B) SIMD
o C) MISD
o D) MIMD Answer: B) SIMD Rationale: SIMD (Single
Instruction, Multiple Data) allows a single instruction to
operate on multiple data points simultaneously,
enhancing performance in data parallelism.
2. In which stage of the instruction pipeline does the
instruction fetch occur?
o A) Decode
o B) Execute
o C) Fetch
o D) Write-back Answer: C)
Fetch Rationale: Instruction fetch is the initial stage in
©2025
, the instruction pipeline, where the processor retrieves an
instruction from memory.
3. What is the primary purpose of cache memory in
computer architecture?
o A) To store the operating system
o B) To speed up data access for the CPU
o C) To reduce power consumption
o D) To increase data storage capacity Answer: B) To
speed up data access for the CPU Rationale: Cache
memory provides faster data access to the CPU by
storing frequently accessed data and instructions.
4. Which of the following is a common measure of processor
performance?
o A) CPU clock speed
o B) Instruction per cycle (IPC)
o C) FLOPS
o D) All of the above Answer: D) All of the
above Rationale: Each of these measures provides
insights into processor performance from different
perspectives, such as speed, efficiency, and throughput.
5. Which of the following architectures utilizes a single bus
to connect all components?
o A) Harvard Architecture
o B) Von Neumann Architecture
o C) RISC Architecture
o D) CISC Architecture Answer: B) Von Neumann
Architecture Rationale: The Von Neumann architecture
uses a single bus for both data and instructions, which
can lead to bottlenecks.
Fill-in-the-Blank Questions
©2025
, 6. The process of breaking down a task into smaller sub-
tasks is known as __________. Answer: Task
Decomposition Rationale: Task decomposition is essential
in parallel computing to enhance efficiency and workload
distribution.
7. The __________ describes the method of accessing
memory either as single or multiple data items in one
operation. Answer: Memory Access Mode Rationale:
Different memory access modes can significantly impact
performance during data retrieval and processing.
8. In pipelined processors, a ________ occurs when an
instruction depends on the result of a previous
instruction. Answer: Data Hazard Rationale: Data hazards
can stall the pipeline, leading to inefficiencies in instruction
processing.
9. The principle of __________ states that no single
instruction affects the execution speed of other
instructions. Answer: Instruction-Level Parallelism
Rationale: Instruction-level parallelism enables multiple
instructions to be executed simultaneously without
interference.
10. The main advantage of using
__________ architecture is the separation of data and
instruction memory. Answer: Harvard Rationale: Harvard
architecture helps in decreasing the bottleneck associated
with the shared bus seen in Von Neumann architecture.
True/False Questions
11. T/F: Parallel computing aims
solely to enhance processing speed. Answer: False
Rationale: While speed is a significant goal, parallel
©2025
