DIGITAL VLSI – HARDWARE SECTION TEST
QUESTIONS AND ANSWERS
What is the difference between a RISC and CISC architecture? - ANSWER ●
RISC architecture has less number of instructions and these instructions are
simple instructions (i.e. fixed-length instructions, and less addressing modes).
On the other hand, CISC architecture has more number of instructions and these
instructions are complex in nature (i.e. variable length instructions, and more
addressing modes). ● RISC approach is to have smaller instructions and less
complex hardware, whereas CISC approach is to have more complex hardware
to decode and break down complex instructions. Hence, In RISC architecture
emphasis is more on software, whereas in CISC architecture emphasis is more
on hardware. ● Since CISC has complex hardware, it requires smaller software
codes and hence less RAM to store programming instructions. As RISC has less
complex hardware, RISC require software programs that uses more number of
instructions and hence more RAM to store instructions. ● Instructions in RISC
architecture usually require one clock cycle to finish, whereas instructions in
CISC architecture can take multiple clock cycles to complete depending upon
the complexity of the instruction. Due to this, pipelining is possible in RISC
architecture.
● RISC architecture aims to improve performance by reducing number of cycles
per instruction whereas CISC architecture attempts to improve performance by
minimizing number of instructions per program. CISC architectures supports
single instruction that can read from memory, do some operation and store back
to memory (known as memory to memory operation). RISC architectures on the
other hand would need multiple instructions to: 1) load the value from memory
to an internal register, 2) perform the intended operation, and 3) write the
register results back to memory. Example: If we have to multiply two numbers
stored at memory locations M1 and M2 and store the result bac
What is the difference between Von-Neumann and Harvard Architecture and
which would you prefer? - ANSWER In Von Neumann architecture, there is a
single memory that can hold both data and instructions. Typically, this would
,mean that there is a single bus from CPU to memory that accesses both data and
instructions. This architecture has a unified cache for both data and instructions.
In Harvard Architecture, memory is separate for data and instructions. There
can be two separate buses to access data and instruction memory
simultaneously. There will also be separate caches for Instruction and Data in
this architecture. The Von Neumann architecture is relatively older and most of
the modern computer architectures are based on Harvard architecture.
Explain the concept of Little Endian and Big Endian formats in terms of
memory storage? - ANSWER Endian-ness refers to the order in which bytes
are stored in a memory (It can also be applicable to digital transmission systems
where it describes the byte order for transmission) Memory is normally byte
addressable but majority of the computer architectures works on 32 bit size or a
word size (4 bytes) operands. Hence, for storing a word into a byte addressable
memory there are two ways: 1) Store the Most significant byte of the word at a
smaller address. This type of storage refers to Big Endian format. 2) Store the
Least significant byte of the word at a smaller address. This type of storage
refers to Little Endian format. For example: If a CPU is trying to write the word
0xDDCCBBAA to an address starting from 0x1000 (address range: 0x1000 to
0x1003), the bytes can be stored in following two different endianness as shown
below.
What is the difference between a SRAM and a DRAM? - ANSWER DRAM
stands for Dynamic Random Access Memory. It is a type of memory in which
the data is stored in the form of a charge. Each memory cell in a DRAM is made
of a transistor and a capacitor. The data is stored in the capacitor. DRAMs are
volatile devices because the capacitor can lose charge due to leakage. Hence, to
keep the data in the memory, the device must be regularly refreshed. On the
other hand, SRAM is a static memory and retains a value as long as power is
supplied. SRAM is typically faster than DRAM since it doesn't have refresh
cycles. Each SRAM memory cell is comprised of 6 Transistors (unlike a
DRAM memory cell which is comprised of 1 Transistor and 1 Capacitor). Due
to this, the cost per memory cell is more for SRAM In terms of usage, SRAMs
, are used in Caches because of higher speed and DRAMs are used for main
memory in a PC because of higher densities.
A computer has a memory of 256 Kilobytes. How many address bits are needed
if each byte location needs to be addressed? - ANSWER Since the total
memory size is 256KB (28*210 Bytes), each address would be eighteen bits
wide.
What are the different types of registers implemented in a CPU? - ANSWER
1) Program Counter (PC): A Program Counter is a register that holds the
address of the instruction being executed currently. 2) Instruction Register (IR):
An Instruction Register is a register that holds the instruction that is currently
getting executed. (It will be value at the address pointed by PC) 3)
Accumulator: An accumulator is a register that holds the intermediate results of
arithmetic and logic operations inside a processor 4) General Purpose Registers:
General Purpose Registers are registers that can store any transient data required
by a program. The number of General purpose registers is defined by the
architecture and these can be used by Software (Assembler) for storing
temporary data during a program execution. More the number of General
Purpose registers, faster will the CPU execution. 5) Stack Pointer Register (SP):
The Stack Pointer Register is a special purpose register that stores the address of
the most recent entry that was pushed on to stack. The most typical use of a
stack is to store the return address of a subroutine call. The SP register helps in
maintaining the top of the Stack Address.
Explain the concept of pipelining in computer architecture? - ANSWER
Pipelining is a technique that implements a form of parallelism called
instruction-level parallelism within a single processor. The basic instruction
cycle is broken up into a series of steps called a pipeline. Rather than processing
each instruction sequentially (finishing one instruction before starting the next),
each instruction is split up into a sequence of steps so different steps can be
executed in parallel and instructions can be processed concurrently (starting one
instruction before finishing the previous one).Pipelining increases instruction
QUESTIONS AND ANSWERS
What is the difference between a RISC and CISC architecture? - ANSWER ●
RISC architecture has less number of instructions and these instructions are
simple instructions (i.e. fixed-length instructions, and less addressing modes).
On the other hand, CISC architecture has more number of instructions and these
instructions are complex in nature (i.e. variable length instructions, and more
addressing modes). ● RISC approach is to have smaller instructions and less
complex hardware, whereas CISC approach is to have more complex hardware
to decode and break down complex instructions. Hence, In RISC architecture
emphasis is more on software, whereas in CISC architecture emphasis is more
on hardware. ● Since CISC has complex hardware, it requires smaller software
codes and hence less RAM to store programming instructions. As RISC has less
complex hardware, RISC require software programs that uses more number of
instructions and hence more RAM to store instructions. ● Instructions in RISC
architecture usually require one clock cycle to finish, whereas instructions in
CISC architecture can take multiple clock cycles to complete depending upon
the complexity of the instruction. Due to this, pipelining is possible in RISC
architecture.
● RISC architecture aims to improve performance by reducing number of cycles
per instruction whereas CISC architecture attempts to improve performance by
minimizing number of instructions per program. CISC architectures supports
single instruction that can read from memory, do some operation and store back
to memory (known as memory to memory operation). RISC architectures on the
other hand would need multiple instructions to: 1) load the value from memory
to an internal register, 2) perform the intended operation, and 3) write the
register results back to memory. Example: If we have to multiply two numbers
stored at memory locations M1 and M2 and store the result bac
What is the difference between Von-Neumann and Harvard Architecture and
which would you prefer? - ANSWER In Von Neumann architecture, there is a
single memory that can hold both data and instructions. Typically, this would
,mean that there is a single bus from CPU to memory that accesses both data and
instructions. This architecture has a unified cache for both data and instructions.
In Harvard Architecture, memory is separate for data and instructions. There
can be two separate buses to access data and instruction memory
simultaneously. There will also be separate caches for Instruction and Data in
this architecture. The Von Neumann architecture is relatively older and most of
the modern computer architectures are based on Harvard architecture.
Explain the concept of Little Endian and Big Endian formats in terms of
memory storage? - ANSWER Endian-ness refers to the order in which bytes
are stored in a memory (It can also be applicable to digital transmission systems
where it describes the byte order for transmission) Memory is normally byte
addressable but majority of the computer architectures works on 32 bit size or a
word size (4 bytes) operands. Hence, for storing a word into a byte addressable
memory there are two ways: 1) Store the Most significant byte of the word at a
smaller address. This type of storage refers to Big Endian format. 2) Store the
Least significant byte of the word at a smaller address. This type of storage
refers to Little Endian format. For example: If a CPU is trying to write the word
0xDDCCBBAA to an address starting from 0x1000 (address range: 0x1000 to
0x1003), the bytes can be stored in following two different endianness as shown
below.
What is the difference between a SRAM and a DRAM? - ANSWER DRAM
stands for Dynamic Random Access Memory. It is a type of memory in which
the data is stored in the form of a charge. Each memory cell in a DRAM is made
of a transistor and a capacitor. The data is stored in the capacitor. DRAMs are
volatile devices because the capacitor can lose charge due to leakage. Hence, to
keep the data in the memory, the device must be regularly refreshed. On the
other hand, SRAM is a static memory and retains a value as long as power is
supplied. SRAM is typically faster than DRAM since it doesn't have refresh
cycles. Each SRAM memory cell is comprised of 6 Transistors (unlike a
DRAM memory cell which is comprised of 1 Transistor and 1 Capacitor). Due
to this, the cost per memory cell is more for SRAM In terms of usage, SRAMs
, are used in Caches because of higher speed and DRAMs are used for main
memory in a PC because of higher densities.
A computer has a memory of 256 Kilobytes. How many address bits are needed
if each byte location needs to be addressed? - ANSWER Since the total
memory size is 256KB (28*210 Bytes), each address would be eighteen bits
wide.
What are the different types of registers implemented in a CPU? - ANSWER
1) Program Counter (PC): A Program Counter is a register that holds the
address of the instruction being executed currently. 2) Instruction Register (IR):
An Instruction Register is a register that holds the instruction that is currently
getting executed. (It will be value at the address pointed by PC) 3)
Accumulator: An accumulator is a register that holds the intermediate results of
arithmetic and logic operations inside a processor 4) General Purpose Registers:
General Purpose Registers are registers that can store any transient data required
by a program. The number of General purpose registers is defined by the
architecture and these can be used by Software (Assembler) for storing
temporary data during a program execution. More the number of General
Purpose registers, faster will the CPU execution. 5) Stack Pointer Register (SP):
The Stack Pointer Register is a special purpose register that stores the address of
the most recent entry that was pushed on to stack. The most typical use of a
stack is to store the return address of a subroutine call. The SP register helps in
maintaining the top of the Stack Address.
Explain the concept of pipelining in computer architecture? - ANSWER
Pipelining is a technique that implements a form of parallelism called
instruction-level parallelism within a single processor. The basic instruction
cycle is broken up into a series of steps called a pipeline. Rather than processing
each instruction sequentially (finishing one instruction before starting the next),
each instruction is split up into a sequence of steps so different steps can be
executed in parallel and instructions can be processed concurrently (starting one
instruction before finishing the previous one).Pipelining increases instruction
