ITE 272 EXAM STUDY QUESTIONS AND ANSWERS

ITE 272 EXAM STUDY QUESTIONS AND ANSWERS fetch - CORRECT ANSWER-data inputs are prepared for transformation into data outputs execution - CORRECT ANSWER-the transformation that takes place and the output is stored control unit (CU) - CORRECT ANSWER-moves data, access instructions, and controls the arithmetic logic unit registers - CORRECT ANSWER-internal storage locations in a CPU; each is capable of holding a single instruction or data item instruction and instruction sets op code - CORRECT ANSWER-the first group of bits and represents the instruction's unique binary number operands - CORRECT ANSWER-In an instruction's bit string, they're groups of bits after the op code that hold the instruction's input values; they can contain a data item or the location of a data item move - CORRECT ANSWER-copies data to storage locations and can copy data between any combination of registers and primary storage locations load - CORRECT ANSWER-data transfer from main memory into a register store - CORRECT ANSWER-data transfer from a register into primary storage unconditional branch - CORRECT ANSWER-changes the sequence of the instruction's execution in the program conditional branch - CORRECT ANSWER-changes the instruction execution only if the value is true halt - CORRECT ANSWER-suspends the normal flow of the program shift - CORRECT ANSWER-moves all values right or left; after shifting, empty positions are filled with 0s, and bit values shifted beyond the bit string's bounds are discarded complex instruction set computing (CISC) - CORRECT ANSWER-a philosophy of processor design that deliberately includes complex instructions in the instruction set reduced instruction set computing (RISC) - CORRECT ANSWER-a philosophy of processor design that limits the number and type of complex instructions in the instruction set clock rate - CORRECT ANSWER-the frequency at which the system clock generates timing pulses cycle time - CORRECT ANSWER-the inverse of clock rate; the time required to fetch and execute the simplest instruction in the instruction set benchmarks - CORRECT ANSWER-measures of CPU or computer performance when carrying out one or more specific tasks; used to compare performance caching - CORRECT ANSWER-storing data in cache memory pipelining - CORRECT ANSWER-A method of organizing CPU circuitry so that multiple instructions can be in different stages of execution at the same time; a form of parallel processing branch prediction - CORRECT ANSWER-An approach to dealing with conditional branches in which the CPU guesses whether a branch condition will be true or false based on past experience; a form of parallel processing speculative execution - CORRECT ANSWER-An approach to dealing with condition branches in which the CPU executes instruction's after a branch prediction but before the final branch condition value is known with certainty; a form of parallel processing multiprocessing - CORRECT ANSWER-any CPU architecture in which duplicate CPUs or processor stages can execute in parallel multicore architecture - CORRECT ANSWER-a microprocessor architecture that embeds multiple CPUs and cache memory on a single chip access time - CORRECT ANSWER-the time required to perform one complete read or write operation blocks - CORRECT ANSWER-a generic term for describing secondary storage data transfer units