Exam (elaborations) VLSI

(T/F) As we scale down the device length of CMOS, the leakage current goes up - ANSTrue (T/F) Diffusion and poly have less resistance than metals - ANSFalse (T/F) Dynamic power is directly proportional to the square of supply voltage - ANSTrue (T/F) Leakage power in VLSI circuit is directly proportional to the frequency - ANSFalse (T/F) NMOS is a good conductor for logic 1 and PMOS is a good conductor for logic 0? - ANSFalse: nFET weak for logic 1 and pFET strong to logic 0. (T/F) RC delay of wire in VLSI design is proportional to the square of the wire length? - ANSTrue (T/F) The logical effort of of NAND3 gate is 5/3? - ANSTrue (T/F) The power in VLSI circuit has linear relation with power supply? - ANSFalse (T/F) The RC delay of a wire is proportional to the square of the length of the wire - ANSTrue (T/F) Wider wires have more resistance - ANSFalse Gate Capacitance (C permicron) is typically about ? fF/um - ANS2 fF/um How are N-type semiconductors created? - ANSby doping an intrinsic semiconductor with an electron donor element during manufacture. Silicon (Si) + arsenic (A) or phosphorous (P) = N-type How are P-type semiconductors created? - ANSby doping an intrinsic semiconductor with an electron acceptor element during manufacture. Silicon (Si) + Boron (Br) = P-type How do you minimize crosstalk? (3 methods) - ANS1) Space out 2) use shielding 3) use different layers of metals If the length of a transistor increases, the current will? - ANSdecrease If the length of a transistor increases, the gate capacitance will? - ANSincrease If the length of CMOS device is scaled down, leakage power will? - ANSincrease If the supply voltage of a chip increases, the gate capacitance of each transistor will? - ANSnot change If the supply voltage of a chip increases, the maximum transistor current will? - ANSincrease If the width of a transistor increases, its gate capacitance will? - ANSincreases In general, what gate is better to use to build a circuit if you have a choice of NAND or NOR gates. Write down at least 3 reasons. - ANS1) smaller overall 2) less leakage 3) add less cap to previous driver Name 4 ways to minimize delay in VLSI Circuits. (Answer has 5) - ANS1) remove unnecessary wires 2) make sure design has balanced efforts 3) widen the wire to reduce resistance 4) add buffer 5) shield wire