Ece385 Midterm 2 Exam Questions With 100% Correct Answers

Ece385 Midterm 2 Exam Questions With 100% Correct Answers SoC includes at least: - answerCPU, memory, peripherals, accelerators soft-IP - answerinstantiated out of SV logic elements NIOS II - answerModified Harvard Machine, 32 bit RISC NIOS II performance is - answerlow compared to the FPGA NIOS memory: - answerno cache memory, largely dependent on RAM PIO module - answerbridge from AVALON to FPGA logic PIO modules may be - answerinput (to software), output (to FPGA fabric), or bidirectional AVALON MM Bus - answer32-bit memory mapped interface BSP (Board Support Package) - answercontains the linker script for SoC TimeQuest will give you - answerlist of worst slack times negative slack = - answerfailed timing Qsys wizard - answerinstantiate IP blocks PLL component - answercompensate for clock skew as SDRAM requires precise timings system ID checker - answerto ensure the compatibility of hardware and software connections our SystemVerilog top-level needs to connect to the appropriate external hardware - answersdram_wire, led_wire, clk, sdram_clk, reset The functionality of the NIOS II processor is that - answerit can run high-level C/C++ on the FPGA board with an accelerator peripheral in the FPGA logic that can handle high performance operations. What advantage might on-chip memory have for program execution? - answerit has a much faster access time to the memory. Note that while the on-chip memory needs access to both the data and program bus, the led peripheral only needs access to the data bus. Why might this be the case? - answerthe LED only needs input to do its function. There is no need for memory or anything for the LED. Why does SDRAM require constant refreshing? - answerthe data is based on the charge of the capacitors on the SDRAM. Without refreshing, data might be lost due to the decay of the charge on the capacitors. Justify how you came up with 1 GBit for memory size. - answerOur SDRAM memory consists if 13 rows, 10 columns of memory with a data width of 32 bits. Other than that, since we have 4 address banks and two 32M * 16 chips, everything adds up to a total of 1Gbit memory size. What is the maximum theoretical transfer rate to the SDRAM according to the timings given? - answerTransfer Time consists of "ACTIVE to READ/WRITE delay" and "Access Time". In the maximum theoretical best case, we would have no active to read/write delay since the data will be already on the chip. Hence, only the memory access time determines the transfer time, which gives us 5.5ns. If we divide 32 bits to 5.5 ns, we get 727 MBps maximum theoretical transfer rate to the SDRAM. The SDRAM cannot be run too slowly (below 50 MHz). Why might this be the case? - answerSDRAM should be synchronised with the clock we use. Since we set the clock to 50 MHz, everything in our circuit should be able to follow that clock The clock going out to the SDRAM chip (clk c1) is 3ns ahead of the controller clock (clk c0). Why do we need to do this? - answerCAS latency is 3 cycles What address does the NIOS II start execution from? - answer0x lab8 - answerCreate low-level interface between NIOS II and USB chip Platform alternatives - answerFull Application, Processor-Centric, Communications-Centric, Highly-Programmable Intellectual Property (IP) - answerBuilding block components (Hard, Firm, Soft) SLC3 parts - answer16 bit data path, 8 register file, ALU, memory instructions, bracnh/jump MEM2IO - answeruses inout ports, MDR/MAR -> mem2IO -> tristate -> tristate -> sram detect load from xFFFF as load from switches, detect store to xFFFF connection between modules a nd SRAM. instantiated in top level