CMPEN 331 – Computer Organization and Design, Lab 5|ALL YOU NEED

Penn State University School of Electrical Engineering and Computer Science Page 1 of 5 CMPEN 331 – Computer Organization and Design, Lab 5 Due Sunday April 28, 2019 at 11:59 pm (Drop box on Canvas) This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first four stages (Instruction Fetch, Instruction Decode, Instruction Execute, Memory) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website. 1. Pipelining As described in lab 4 2. Circuits of the Instruction Fetch Stage As described in lab 4 3. Circuits of the Instruction Decode Stage As described in lab 4 4. Circuits of the Execution Stage As described in lab 5 5. Circuits of the Memory Access Stage As described in lab 5 6. Circuits of the Write Back Stage Referring to Figure 1, in the fifth cycle the first instruction entered the WB stage. The memory data is selected and will be written into the register fi