System Verilog for Verification
Chapter 1
, Contents
➢ Introduction
➢ Verification guidelines
,Introduction
SystemVerilog can be divided into two distinct based on its
roles,
SystemVerilog for design is an extension of Verilog-2005
SystemVerilog for verification
, SystemVerilog Components
SystemVerilog language is a combination of concepts of
multiple languages.
SystemVerilog language components are,
Concepts of Verilog HDL
Testbench constructs based on Vera
OpenVera assertions
Synopsys’ VCS DirectC simulation interface to C and C++
A coverage application programming interface that provides
links to coverage metrics
Chapter 1
, Contents
➢ Introduction
➢ Verification guidelines
,Introduction
SystemVerilog can be divided into two distinct based on its
roles,
SystemVerilog for design is an extension of Verilog-2005
SystemVerilog for verification
, SystemVerilog Components
SystemVerilog language is a combination of concepts of
multiple languages.
SystemVerilog language components are,
Concepts of Verilog HDL
Testbench constructs based on Vera
OpenVera assertions
Synopsys’ VCS DirectC simulation interface to C and C++
A coverage application programming interface that provides
links to coverage metrics
