Exam (elaborations) TEST BANK FOR The 8088 and 8086 Microprocessors Programming, Interfacing, Software, Hardware, and Applications 4th Edition By Walter A. Triebel (Instructor's Solution Manual)

Exam (elaborations) TEST BANK FOR The 8088 and 8086 Microprocessors Programming, Interfacing, Software, Hardware, and Applications 4th Edition By Walter A. Triebel (Instructor's Solution Manual) Instructor's Solution Manual with Transparency Masters THE 8088 AND 8086 MICROPROCESSORS Programming, Interfacing, Software, Hardware, and Applications Fourth Edition Walter A. Triebel Fairliegh Dickinson University Avtar Singh San Jose State University Including the 80286, 80386, 80486, and PentiumTM Processors CONTENTS Chapter Page 1 Introduction to Microprocessors and Microcomputers 4 2 Software Architecture of the 8088 and 8086 Microprocessors 5 3 Assembly Language Programming 9 4 Machine Language Coding and the DEBUG Software Development 11 Program of the PC 5 8088/8086 Programming—Integer Instructions and Computations 16 6 8088/8086 Programming—Control Flow Instructions and Program 23 Structures 7 Assembly Language Program Development with MASM 33 8 The 8088 and 8086 Microprocessors and their Memory 35 and Input/Output Interfaces 9 Memory Devices, Circuits, and Subsystem Design 42 10 Input/Output Interface Circuits and LSI Peripheral Devices 49 11 Interrupt Interface of the 8088 and 8086 Microprocessors 55 12 Hardware of the Original IBM PC Microcomputer 58 13 PC Bus Interfacing, Circuit Construction, Testing, and 63 Troubleshooting 14 Real-Mode Software and Hardware Architecture of the 80286 68 Microprocessor 15 The 80386, 80486, and PentiumR Processor Families: Software 71 Architecture 16 The 80386, 80486, and PentiumR Processor Families: Hardware 77 Architecture CHAPTER 1 Section 1.1 1. Original IBM PC. 2. A system whose functionality expands by simply adding special function boards. 3. I/O channel. 4. Personal computer advanced technology. 5. Industry standard architecture. 6. Peripheral component interface (PCI) bus 7. A reprogrammable microcomputer is a general-purpose computer designed to run programs for a wide variety of applications, for instance, accounting, word processing, and languages such as BASIC. 8. Mainframe computer, minicomputer, and microcomputer. 9. The microcomputer is similar to the minicomputer in that it is designed to perform general-purpose data processing; however, it is smaller in size, has reduced capabilities, and cost less than a minicomputer. 10. Very large scale integration. Section 1.2 11. Input unit, output unit, microprocessing unit, and memory unit. 12. Microprocessing unit (MPU). 13. 16-bit. 14. Keyboard; mouse and scanner. 15. Monitor and printer. 16. Primary storage and secondary storage memory. 17. 360K bytes; 10M bytes. 18. Read-only memory (ROM) and random access read/write memory (RAM). 19. 48K bytes; 256K bytes. 20. The Windows98R program is loaded from the hard disk into RAM and then run. Since RAM is volatile, the operating system is lost whenever power is turned off. Section 1.3 21. 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit. 22. 4004, 8008, 8086, 80386DX. 23. 8086, 8088, 80186, 80188, 80286. 24. Million instructions per second. 25. 27 MIPS 26. Drystone program. 27. 39; 49. 28. 30,000, 140,000, 275,000, 1,200,000, 3,000,000. 29. A special purpose microcomputer that performs a dedicated control function. 30. Event controller and data controller. 31. A multichip microcomputer is constructed from separate MPU, memory, and I/O ICs. On the other hand, in a single chip microcomputer, the MPU, memory, and I/O functions are all integrated into one IC. 32. 8088, 8086, 80286, 80386DX, 80486DX, and PentiumR processor. 33. Real mode and protected mode. 34. Upward software compatible means that programs written for the 8088 or 8086 will run directly on the 80286, 80386DX, and 80486DX. 35. Memory management, protection, and multitasking. 36. Floppy disk controller, communication controller, and local area network controller. Section 1.4 37. MSB and LSB. 38. 2-2 = 1/4 39. 1 and 2+5 = 1610; 1 and 2-4 = 1/16 40. (a) 610, (b) 2110, (c) 12710. 41. Min = = 010, Max = = 25510. 42. (a) , (b) , (c) 43. 44. (a) .12 (b) .012 (c) . 45. C and 16+2 = 25610 46. 16+4 = 65,53610 47. (a) 39H, (b) E2H, (c) 03A0H. 48. (a) , (b) , (c) . 49. C6H, 19810. 50. MSB = 1, LSB = 0. 51. 8005AH, 1,048,66610. CHAPTER 2 Section 2.1 1. Bus interface unit and execution unit. 2. BIU. 3. 20 bits; 16 bits. 4. 4 bytes; 6 bytes. 5. General-purpose registers, temporary operand registers, arithmetic logic unit (ALU), and status and control flags. Section 2.2 6. Aid to the assembly language programmer for understanding a microprocessor's software operation. 7. There purpose, function, operating capabilities, and limitations. 8. 14 9. 1,048,576 (1M) bytes. 10. 65,536 (64K) bytes. Section 2.3 11. FFFFF16 and . 12. Bytes. 13. 00FF16; aligned word. 14. 6; misaligned double word. 15. Address Contents 0A003H CDH 0A004H ABH aligned word. 16. Address Contents 0A001H 78H 0A002H 56H 0A003H 34H 0A004H 12H misaligned double word. Section 2.4 17. Unsigned integer, signed integer, unpacked BCD, packed BCD, and ASCII. 18. (a) 7FH (b) F6H (c) 80H (d) 01F4H 19. (0A000H) = F4H (0A001H) = 01H 20. -1000 = 2's complement of 1000 = FC18H 21. (a) , ; (b) , ; 22. (0B000H) = 09H (0B001H) = 02H 23. NEXT I 24. (0C000H) = 34H (0C001H) = 33H (0C002H) = 32H (0C003H) = 31H Section 2.5 25. 64Kbytes. 26. Code segment (CS) register, stack segment (SS) register, data segment (DS) register, and extra segment (ES) register. 27. CS. 28. Up to 256Kbytes. 29. Up to 128Kbytes. Section 2.6 30. Pointers to interrupt service routines. 31. 8016 through FFFEF16. 32. Instructions of the program can be stored anywhere in the general-use part of the memory address space. 33. Control transfer to the reset power-up initialization software routine. Section 2.7 34. The instruction pointer is the offset address of the next instruction to be fetched by the 8088 relative to the current value in CS. 35. The instruction is fetched from memory; decoded within the 8088; operands are read from memory or internal registers; the operation specified by the instruction is performed on the data; and results are written back to either memory or an internal register. 36. IP is incremented such that it points to the next sequential word of instruction code. Section 2.8 37. Accumulator (A) register, base (B) register, count (C) register, and data (D) register. 38. With a postscript X to form AX, BX, CX, and DX. 39. DH and DL. 40. Count for string operations and count for loop operations. Section 2.9 41. Offset address of a memory location relative to a segment base address. 42. Base pointer (BP) and stack pointer (SP). 43. SS 44. DS 45. Source index register; destination index register. 46. The address in SI is the offset to a source operand and DI contains the offset to a destination operand. Section 2.10 47. Flag Type CF Status PF Status AF Status ZF Status SF Status OF Status TF Control IF Control DF Control 48. CF = 1, if a carry-out/borrow-in results for the MSB during the execution of an arithmetic instruction. Else it is 0. PF = 1, if the result produced by execution of an instruction has even parity. Else it is 0. AF = 1, if there is a carry-out/borrow-in for the fourth bit during the execution of an arithmetic instruction. ZF = 1, if the result produced by execution of an instruction is zero. Else it is 0. SF = 1, if the result produced by execution of an instruction is negative. Else it is 0. OF = 1, if an overflow condition occurs during the execution of an arithmetic instruction. Else it is 0. 49. Instructions can be used to test the state of these flags and, based on their setting, modify the sequence in which instructions of the program are executed. 50. Trap flag 51. DF 52. Instructions are provided that can load the complete register or modify specific flag bits. Section 2.11 53. 20 bits. 54. Offset and segment base. 55. (a) 11234H (b) 0BBCDH (c) A32CFH (d) C2612H 56. (a) ? = 0123H (b) ? = 2210H (c) ? = 3570H (d) ? = 2600H 57. 021AC16 58. A00016 59. Section 2.12 60. The stack is the area of memory used to temporarily store information (parameters) to be passed to subroutines and other information such as the contents of IP and CS that is needed to return from a called subroutine to the main part of the program. 61. CFF0016 62. 128 words. 63. FEFEH ® (SP) (AH) = EEH ® (CFEFFH) (AL) = 11H ® (CFEFEH) Section 2.13 64. Separate. 65. 64-Kbytes. 66. Page 0. CHAPTER 3 Section 3.1 1. Software. 2. Program. 3. Operating system. 4. 80386DX machine code. 5. Instructions encoded in machine language are coded in 0s and 1s, while assembly language instructions are written with alphanumeric symbols such as MOV, ADD, or SUB. 6. Mnemonic that identifies the operation to be performed by the instruction; ADD and MOV. 7. The data that is to be processed during execution of an instruction; source operand and destination operand. 8. START; ;Add BX to AX 9. An assembler is a program that is used to convert an assembly language source program to its equivalent program in machine code. A compiler is a program that converts a program written in a high-level language to equivalent machine code. 10. Programs written is assembly language or high level language statements are called source code. The machine code output of an assembler or compiler is called object code. 11. It takes up less memory and executes faster. 12. A real-time application is one in which the tasks required by the application must be completed before any other input to the program occurs that can alter its operation. 13. Floppy disk subsystem control and communications to a printer; code translation and table sort routines. Section 3.2 14. Application specification. 15. Algorithm; software specification. 16. A flowchart is a pictorial representation that outlines the software solution to a problem. 17. 18. Editor. 19. Assembler. 20. Macroassembler. 21. Linker. 22. (a) Creating a source program (b) Assembling a source program into an object module (c) Producing a run module (d) Verifying/debugging a solution 23. (a) PROG_A.ASM (b) PROG_A.LST and PROG_A.OBJ (c) PROG_A.EXE and PROG_A.MAP Section 3.3 24. 117. 25. Data transfer instructions, arithmetic instructions, logic instructions, string manipulation instructions, control transfer instructions, and processor control instructions. Section 3.4 26. Execution of the move instruction transfers a byte or a word of data from a source location to a destination location. Section 3.5 27. An addressing mode means the method by which an operand can be specified in a register or a memory location. 28. Register operand addressing mode Immediate operand addressing mode Memory operand addressing modes 29. Base, index, and displacement. 30. Direct addressing mode Register indirect addressing mode Based addressing mode Indexed addressing mode Based-indexed addressing mode 31. Instruction Destination Source (a) Register Register (b) Register Immediate (c) Register indirect Register (d) Register Register indirect (e) Based Register (f) Indexed Register (g) Based-indexed Register 32. (a) PA = 0B20016 (b) PA = 0B10016 (c) PA = 0B70016 (d) PA = 0B60016 (e) PA = 0B90016 CHAPTER 4 Section 4.1 1. 6 bytes. 2. = 03C2H 3. (a) = 8915H; (b) = 8918H; (c) = 8A5710H 4. (a) = 1EH; (b) = D2C3H; (c) = H Section 4.2 5. 3 bytes. 6. 24 bytes. Section 4.3 7. The DEBUG program allows us to enter a program into the PC's memory, execute it under control, view its operation, and modify it to fix errors. 8. Yes. 9. Error. 10. -R CX (¿) CX XXXX :0010 (¿) 11. -R F (¿) NV UP EI PL NZ NA PO NC -PE (¿) 12. -R (¿) Section 4.4 13. -D CS:0000 000F (¿) 14. -E CS:0 (¿) 1342:0000 CD. 20. 00. 40. 00. 9A. EE. FE. 1342:0008 1D. F0. F5. 02. A7. 0A. 2E. 03. (¿) After a byte of data is displayed, the space bar is depressed to display the next byte. The values displayed may not be those shown but will be identical to those displayed with the DUMP command. 15. -E CS:100 FF FF FF FF FF (¿) 16. -E SS:(SP) 0 ......0 (32 zeros) (¿) 17. -F CS: (¿) -F CS:106 10B 22 (¿) -F CS:10C 111 33 (¿) -F CS: (¿) -F CS:118 11D 55 (¿) -E CS:105 (¿) CS:0105 XX.FF (¿) -E CS:113 (¿) -CS:0113 XX.FF (¿) -D CS:100 11D (¿) -S CS:100 11D FF (¿) Section 4.5 18. Input command and output command. 19. Contents of the byte-wide input port at address is input and displayed on the screen. 20. O 124 5A (¿) Section 4.6 21. The sum and difference of two hexadecimal numbers. 22. 4 digits. 23. H FA 5A (¿) Section 4.7 24. -E CS:100 32 0E 34 12 (¿) -U CS:100 103 (¿) 1342:100 320E3412 XOR CL,[1234] -W CS:100 1 50 1 (¿) 25. -L CS:400 1 50 1 (¿) -U CS:400 403 (¿) 1342:0400 320E3412 XOR CL,[1234] - Section 4.8 26. -A CS:100 (¿) 1342:0100 MOV [DI],DX (¿) 1342:0102 (¿) 27. -A CS:200 (¿) 1342:0200 ROL BL,CL (¿) 1342:0202 (¿) -U CS:200 201 (¿) 1342:0200 D2C3 ROL BL,CL - Section 4.9 28. -L CS:300 1 50 1 (¿) -U CS:300 303 (¿) -R CX (¿) CX XXXX :000F (¿) -E DS:1234 FF (¿) -T =CS:300 (¿) -D DS: (¿) 29. -N A:BLK.EXE (¿) -L CS:200 (¿) -R DS (¿) DS 1342 :2000 (¿) -F DS:100 10F FF (¿) -F DS:120 12F 00 (¿) -D DS:100 10F (¿) 2000:0100 FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF -D DS:120 12F (¿) 2000: - 00 00 00 -R DS (¿) DS 2000 :1342 (¿) -R (¿) AX=0000 BX=0000 CX=0000 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000 DS=1342 ES=1342 SS=1342 CS=1342 IP=0100 NV UP EI PL NZ NA PO NC 1342: MOV [DI],DX DS:0000=20CD -U CS:200 217 (¿) 1342:0200 B80020 MOV AX,2000 1342:0203 8ED8 MOV DS,AX 1342:0205 BE0001 MOV SI,0100 1342:0208 BF2001 MOV DI,0120 1342:020B B91000 MOV CX,0010 1342:020E 8A24 MOV AH,[SI] 1342: MOV [DI],AH 1342:0212 46 INC SI 1342:0213 47 INC DI 1342:0214 49 DEC CX 1342:0215 75F7 JNZ 020E 1342:0217 90 NOP -G =CS:200 217 (¿) AX=FF00 BX=0000 CX=0000 DX=0000 SP=FFEE BP=0000 SI=0110 DI=0130 DS=2000 ES=1342 SS=1342 CS=1342 IP=0217 NV UP EI PL ZR NA PE NC 1342:0217 90 NOP -D DS:100 10F (¿) 2000:0100 FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF -D DS:120 12F (¿) 2000:0120 FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF Section 4.10 30. A syntax error is an error in the rules of coding the program. On the other hand, an execution error is an error in the logic of the planned solution for the problem. 31. Bugs. 32. Debugging the program. 33. -N A:BLK.EXE (¿) -L CS:200 (¿) -U CS:200 217 (¿) 1342:0200 B80020 MOV AX,2000 1342:0203 8ED8 MOV DS,AX 1342:0205 BE0001 MOV SI,0100 1342:0208 BF2001 MOV DI,0120 1342:020B B91000 MOV CX,0010 1342:020E 8A24 MOV AH,[SI] 1342: MOV [DI],AH 1342:0212 46 INC SI 1342:0213 47 INC DI 1342:0214 49 DEC CX 1342:0215 75F7 JNZ 020E 1342:0217 90 NOP -R DS (¿) DS 1342 :2000 (¿) -F DS:100 10F FF (¿) -F DS:120 12F 00 (¿) -R DS (¿) DS 2000 :1342 (¿) -G =CS:200 20E (¿) AX=2000 BX=0000 CX=0010 DX=0000 SP=FFEE BP=0000 SI=0100 DI=0120 DS=2000 ES=1342 SS=1342 CS=1342 IP=020E NV UP EI PL NZ NA PO NC 1342:020E 8A24 MOV AH,[SI] DS:0100=FF -D DS:120 12F (¿) 2000: - 00 00 00 -G 212 (¿) AX=FF00 BX=0000 CX=0010 DX=0000 SP=FFEE BP=0000 SI=0100 DI=0120 DS=2000 ES=1342 SS=1342 CS=1342 IP=0212 NV UP EI PL NZ NA PO NC 1342:0212 46 INC SI -D DS:120 12F (¿) 2000:0120 FF 00 00- 00 00 00 -G 215 (¿) AX=FF00 BX=0000 CX=000F DX=0000 SP=FFEE BP=0000 SI=0101 DI=0121 DS=2000 ES=1342 SS=1342 CS=1342 IP=0215 NV UP EI PL NZ AC PE NC 1342:0215 75F7 JNZ 020E -G 20E (¿) AX=FF00 BX=0000 CX=000F DX=0000 SP=FFEE BP=0000 SI=0101 DI=0121 DS=2000 ES=1342 SS=1342 CS=1342 IP=020E NV UP EI PL NZ AC PE NC 1342:020E 8A24 MOV AH,[SI] DS:0101=FF -G 215 (¿) AX=FF00 BX=0000 CX=000E DX=0000 SP=FFEE BP=0000 SI=0102 DI=0122 DS=2000 ES=1342 SS=1342 CS=1342 IP=0215 NV UP EI PL NZ NA PO NC 1342:0215 75F7 JNZ 020E -D DS:120 12F (¿) 2000:0120 FF FF 00- 00 00 00 -G 20E (¿) AX=FF00 BX=0000 CX=000E DX=0000 SP=FFEE BP=0000 SI=0102 DI=0122 DS=2000 ES=1342 SS=1342 CS=1342 IP=020E NV UP EI PL NZ NA PO NC 1342:020E 8A24 MOV AH,[SI] DS:0102=FF -G 217 (¿) AX=FF00 BX=0000 CX=0000 DX=0000 SP=FFEE BP=0000 SI=0110 DI=0130 DS=2000 ES=1342 SS=1342 CS=1342 IP=0217 NV UP EI PL ZR NA PE NC 1342:0217 90 NOP -D DS:120 12F (¿) 2000:0120 FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF CHAPTER 5 Section 5.1 1. (a) Value of immediate operand 0110H is moved into AX. (b) Contents of AX are copied into DI. (c) Contents of AL are copied into BL. (d) Contents of AX are copied into memory address DS:0100H. (e) Contents of AX are copied into the data segment memory location pointed to by (DS)0 + (BX) + (DI). (f) Contents of AX are copied into the data segment memory location pointed to by (DS)0 + (DI) + 4H. (g) Contents of AX are copied into the data segment memory location pointed to by (DS)0 + (BX) + (DI) + 4H. 2. (a) Value 0110H is moved into AX. (b) 0110H is copied into DI.