ECEN 350 FINAL QUESTIONS & ANSWERS
1. (True or False) The following is the complete RTL description of the "AND"
instruction- answer -
R[rd] = R[rs] & R[rt];- answer - False
2. Adding two ports to an SRAM means increasing each cell by
transistors. (how many?)- answer - 4
3. Fetch, and Execute are the three phases of an instructions life-cycle.-
- answer - decode
4. For all D-Type instructions, Read Data 2 is connected to the ALU.- answer - False
5. Hardware that is not in use for a given instruction (on the unified hardware) is
removed until needed to save power.- answer - False
6. RTL defines the actions of an instruction in terms of operations performed on
registers, with the outcome being placed in another register.- answer - True
7. RTL stands for .- answer - register transfer language
8. The B instruction does not require the registerfile at all.- answer - True
9. The fastest path through the logic determines its critical path and hence its clock
frequency.- answer - False
10. The register file must have three ports (two read and one write) in order to
directly support D-Type instructions.- answer - False
11. There are many different possible implementations of a particular ISA in
hardware.- answer - True
12. are used to allow for different inputs to a given piece of hardware
when it requires different inputs when used by different instructions. For ex-
ample, it is used on the input to the registerfile's Write Address input to select
between Rd and Rt depending on which instruction is executing.- answer - multiplexers
13. For all R-Type instruction, Read Data 2 is connected to the ALU.- answer - True
,14. In the LDUR and STUR instructions, the ALU is used for effective
calculation.- answer - address
15. The registerfile does not produce any output on Read Data 1 and Read Data 2 for
the B instruction.- answer - False
16. Assuming Fetch has placed an instruction on the bus called I[31- answer -0] (in
Verilog notation), which wires should be connected to "Read Addr 2" on the register file
for the proper execution of R-Type instructions.- answer - I[20- answer -16]
, 17. For the CBZ instruction, the ALU must be set to perform the "pass
18. In the figure below, fill in the control unit signal outputs for the microarchi-
tecture when the following instruction is executed- answer -
ADD X1, X2, 0x10- answer - Reg2Loc = x
SignOp = I-
Type
Uncondbranch =
0
Branch = 0
MemRead = 0
M
e
m
t
o
R
e
g
=
0
A
L
U
O
1. (True or False) The following is the complete RTL description of the "AND"
instruction- answer -
R[rd] = R[rs] & R[rt];- answer - False
2. Adding two ports to an SRAM means increasing each cell by
transistors. (how many?)- answer - 4
3. Fetch, and Execute are the three phases of an instructions life-cycle.-
- answer - decode
4. For all D-Type instructions, Read Data 2 is connected to the ALU.- answer - False
5. Hardware that is not in use for a given instruction (on the unified hardware) is
removed until needed to save power.- answer - False
6. RTL defines the actions of an instruction in terms of operations performed on
registers, with the outcome being placed in another register.- answer - True
7. RTL stands for .- answer - register transfer language
8. The B instruction does not require the registerfile at all.- answer - True
9. The fastest path through the logic determines its critical path and hence its clock
frequency.- answer - False
10. The register file must have three ports (two read and one write) in order to
directly support D-Type instructions.- answer - False
11. There are many different possible implementations of a particular ISA in
hardware.- answer - True
12. are used to allow for different inputs to a given piece of hardware
when it requires different inputs when used by different instructions. For ex-
ample, it is used on the input to the registerfile's Write Address input to select
between Rd and Rt depending on which instruction is executing.- answer - multiplexers
13. For all R-Type instruction, Read Data 2 is connected to the ALU.- answer - True
,14. In the LDUR and STUR instructions, the ALU is used for effective
calculation.- answer - address
15. The registerfile does not produce any output on Read Data 1 and Read Data 2 for
the B instruction.- answer - False
16. Assuming Fetch has placed an instruction on the bus called I[31- answer -0] (in
Verilog notation), which wires should be connected to "Read Addr 2" on the register file
for the proper execution of R-Type instructions.- answer - I[20- answer -16]
, 17. For the CBZ instruction, the ALU must be set to perform the "pass
18. In the figure below, fill in the control unit signal outputs for the microarchi-
tecture when the following instruction is executed- answer -
ADD X1, X2, 0x10- answer - Reg2Loc = x
SignOp = I-
Type
Uncondbranch =
0
Branch = 0
MemRead = 0
M
e
m
t
o
R
e
g
=
0
A
L
U
O
