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WGU C952
Computer Architecture - Set 5 Exam All In One, 50 Multiple
Choice Questions And Answers ( Verified Answers), 100%
Guaranteed Pass ||Complete A+ Guide
This Document Contains:
WGU C952 Computer Architecture
Set 5 Exam
50 Multiple Choice Questions And Answers
100% Guaranteed Pass
,C952 Computer Architecture - Set 5 - Part 1
Question 1: Which cache replacement policy selects the cache block that has been
unused for the longest time?
Random replacement
Least Recently Used (LRU)
First-In-First-Out (FIFO)
Most Recently Used (MRU)
Answer: Least Recently Used (LRU)
LRU replacement policy removes the block that has not been accessed for the longest
time, assuming it is least likely to be used soon.
Question 2: What is the purpose of a "frame pointer" in assembly language?
Holds the address of the current program instruction
Points to the beginning of the current function’s stack frame
Tracks the most recently allocated memory
Stores global variables
Answer: Points to the beginning of the current function’s stack frame
The frame pointer holds the base of the stack frame for the current function, aiding in
the organization of function calls and local variables.
Question 3: In a RAID array, which level combines both parity and striping to
achieve fault tolerance and high performance?
RAID 0
RAID 1
RAID 5
RAID 10
, C952 Computer Architecture - Set 5 - Part 1
Answer: RAID 5
RAID 5 uses both parity for fault tolerance and striping for performance, balancing
redundancy and speed.
Question 4: What is the term for an on/off switch that is controlled by an electric
signal in a computer chip?
ALU
Transistor
Clock signal
Interrupt
Answer: Transistor
A transistor acts as an electronic switch within a computer, controlled by signals to
manage data flow in logic circuits.
Question 5: What does a "miss penalty" refer to in cache memory systems?
The time to access main memory after a cache miss
The delay from branch instructions
The penalty for unused cache memory
The rate of compulsory misses
Answer: The time to access main memory after a cache miss
Miss penalty is the time needed to fetch data from main memory when it is not found
in the cache, impacting performance.
Question 6: Which type of cache has separate areas for instructions and data,
optimizing access speed?
Unified cache
Write-through cache
WGU C952
Computer Architecture - Set 5 Exam All In One, 50 Multiple
Choice Questions And Answers ( Verified Answers), 100%
Guaranteed Pass ||Complete A+ Guide
This Document Contains:
WGU C952 Computer Architecture
Set 5 Exam
50 Multiple Choice Questions And Answers
100% Guaranteed Pass
,C952 Computer Architecture - Set 5 - Part 1
Question 1: Which cache replacement policy selects the cache block that has been
unused for the longest time?
Random replacement
Least Recently Used (LRU)
First-In-First-Out (FIFO)
Most Recently Used (MRU)
Answer: Least Recently Used (LRU)
LRU replacement policy removes the block that has not been accessed for the longest
time, assuming it is least likely to be used soon.
Question 2: What is the purpose of a "frame pointer" in assembly language?
Holds the address of the current program instruction
Points to the beginning of the current function’s stack frame
Tracks the most recently allocated memory
Stores global variables
Answer: Points to the beginning of the current function’s stack frame
The frame pointer holds the base of the stack frame for the current function, aiding in
the organization of function calls and local variables.
Question 3: In a RAID array, which level combines both parity and striping to
achieve fault tolerance and high performance?
RAID 0
RAID 1
RAID 5
RAID 10
, C952 Computer Architecture - Set 5 - Part 1
Answer: RAID 5
RAID 5 uses both parity for fault tolerance and striping for performance, balancing
redundancy and speed.
Question 4: What is the term for an on/off switch that is controlled by an electric
signal in a computer chip?
ALU
Transistor
Clock signal
Interrupt
Answer: Transistor
A transistor acts as an electronic switch within a computer, controlled by signals to
manage data flow in logic circuits.
Question 5: What does a "miss penalty" refer to in cache memory systems?
The time to access main memory after a cache miss
The delay from branch instructions
The penalty for unused cache memory
The rate of compulsory misses
Answer: The time to access main memory after a cache miss
Miss penalty is the time needed to fetch data from main memory when it is not found
in the cache, impacting performance.
Question 6: Which type of cache has separate areas for instructions and data,
optimizing access speed?
Unified cache
Write-through cache
