CHAPTER 12 DIGITAL LOGIC
ANSWERS TO PROBLEMS
12.1
A B C a b c d
0 0 0 1 1 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 1
1 0 0 0 1 0 1
1 0 1 0 0 1 1
1 1 0 0 0 1 0
1 1 1 1 1 0 0
12.2 Recall the commutative law: AB = BA; A+B=B+A
a. AB + CDE + C DE
b. AB + AC
c. (LMN) (AB) (CDE)
d. F (K + R) + SV + W X
@
12.3 a. F = V • A •L . This is just a generalization of DeMorgan's Theorem,
and is easily proved.
Ap
b. F = ABCD . Again, this is a generalization of DeMorgan's Theorem.
12.4 a. A = ST + VW
b. A = TUV + Y
lu
c. A=F
d. A = ST
e. A = D + E
s
f. A = YZ (W + X +YZ) = YZ
st
g. A = C
12.5 A XOR B = A B + A B
uv
ia
@Testbanksmafia
,12.6 ABC = NOR ( A , B , C )
12.7 Y = NAND (A, B, C, D) = ABCD
12.8 a.
X1 X2 X3 X4 Z1 Z2 Z3 Z4 Z5 Z6 Z7
0 0 0 0 1 1 1 0 1 1 1
0 0 0 1 0 0 1 0 0 1 0
0 0 1 0 1 0 1 1 1 0 1
0 0 1 1 1 0 1 1 0 1 1
0 1 0 0 0 1 1 1 0 1 0
0 1 0 1 1 1 0 1 0 1 1
0 1 1 0 0 1 0 1 1 1 1
0 1 1 1 1 0 1 0 0 1 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 0
1 0 1 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
@
b. All of the terms have the form illustrated as follows:
Z5 = X1X2X3X4 + X1X2 X3 X4 + X1 X2X3 X4 + X1 X2X3X4
Ap
c. Whereas the SOP form lists all combinations that produce an output
of 1, the POS lists all combinations that produce an output of 0.
For example,
lu
Z3 = ( X1 X2 X3 X4) ( X1 X2X3 X4 )
s
= (X1 X2 X3 X4 ) (X1 X2 X3 X4)
st
uv
ia
@Testbanksmafia
,12.9 Label the 8 inputs I0, ... , I7, the select lines S0, S1, S2., and the
output line F.
F=Io S0 S1S2 + I1S0S1S2 + I2 S0S1S2 + I3S0S1S2 + I4S0 S1S2 + I5S0 S1S2 + I6S0S1S2 + I7S0S1S2
12.10 Add a data input line and connect it to the input side of each AND
gate.
12.11 Define the input leads as B2, B1, B0 and the output leads as G2, G1,
G0. Then
G2 = B2
G1 = B2 B1 + B2 B1
G0 = B1B0 + B1B0
12.12 The Input is A4A3A2A1A0. Use A2A1A0 as the input to each of the 3
8 decoders. There are a total of 32 outputs from these four 3 8
decoders. Use A4A3 as input to a 2 4 decoder and have the four
outputs go to the enable leads of the four 3 8 decoders. The result
is that one and only one of the 32 outputs will have a value of 1.
12.13 SUM = A B C
CARRY = AB AC BC
12.14 a. The carry to the second stage is available after 20 ns; the carry
to the third stage is available 20 ns after that, and so on. When
the carry reaches the 32nd stage, another 20 ns are needed to
produce the final sum. Thus
@
T = 31 20 + 20 = 640 ns
Ap
b. Each 8-bit adder produces a sum in 30 ns and a carry in 20 ns.
Therefore,
T = 3 20 + 20 = 80 ns
lu
s st
uv
ia
@Testbanksmafia
, 12.15 a.
Characteristic table Simplified characteristic
table
Current Current Next S R Qn+1
input state state
SR Qn Qn+1
00 0 — 0 0 —
00 1 — 0 1 1
01 0 1 1 0 0
01 1 1 1 1 Qn
10 0 0
10 1 0
11 0 0
11 1 1
b.
t 0 1 2 3 4 5 6 7 8 9
S 0 1 1 1 1 1 0 1 0 1
R 1 1 0 1 0 1 1 1 0 0
Qn 0 0 1 1 1 1 0 0 — 1
12.16
@
Ap
lu
s st
uv
ia
@Testbanksmafia
ANSWERS TO PROBLEMS
12.1
A B C a b c d
0 0 0 1 1 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 1
1 0 0 0 1 0 1
1 0 1 0 0 1 1
1 1 0 0 0 1 0
1 1 1 1 1 0 0
12.2 Recall the commutative law: AB = BA; A+B=B+A
a. AB + CDE + C DE
b. AB + AC
c. (LMN) (AB) (CDE)
d. F (K + R) + SV + W X
@
12.3 a. F = V • A •L . This is just a generalization of DeMorgan's Theorem,
and is easily proved.
Ap
b. F = ABCD . Again, this is a generalization of DeMorgan's Theorem.
12.4 a. A = ST + VW
b. A = TUV + Y
lu
c. A=F
d. A = ST
e. A = D + E
s
f. A = YZ (W + X +YZ) = YZ
st
g. A = C
12.5 A XOR B = A B + A B
uv
ia
@Testbanksmafia
,12.6 ABC = NOR ( A , B , C )
12.7 Y = NAND (A, B, C, D) = ABCD
12.8 a.
X1 X2 X3 X4 Z1 Z2 Z3 Z4 Z5 Z6 Z7
0 0 0 0 1 1 1 0 1 1 1
0 0 0 1 0 0 1 0 0 1 0
0 0 1 0 1 0 1 1 1 0 1
0 0 1 1 1 0 1 1 0 1 1
0 1 0 0 0 1 1 1 0 1 0
0 1 0 1 1 1 0 1 0 1 1
0 1 1 0 0 1 0 1 1 1 1
0 1 1 1 1 0 1 0 0 1 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 0
1 0 1 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
@
b. All of the terms have the form illustrated as follows:
Z5 = X1X2X3X4 + X1X2 X3 X4 + X1 X2X3 X4 + X1 X2X3X4
Ap
c. Whereas the SOP form lists all combinations that produce an output
of 1, the POS lists all combinations that produce an output of 0.
For example,
lu
Z3 = ( X1 X2 X3 X4) ( X1 X2X3 X4 )
s
= (X1 X2 X3 X4 ) (X1 X2 X3 X4)
st
uv
ia
@Testbanksmafia
,12.9 Label the 8 inputs I0, ... , I7, the select lines S0, S1, S2., and the
output line F.
F=Io S0 S1S2 + I1S0S1S2 + I2 S0S1S2 + I3S0S1S2 + I4S0 S1S2 + I5S0 S1S2 + I6S0S1S2 + I7S0S1S2
12.10 Add a data input line and connect it to the input side of each AND
gate.
12.11 Define the input leads as B2, B1, B0 and the output leads as G2, G1,
G0. Then
G2 = B2
G1 = B2 B1 + B2 B1
G0 = B1B0 + B1B0
12.12 The Input is A4A3A2A1A0. Use A2A1A0 as the input to each of the 3
8 decoders. There are a total of 32 outputs from these four 3 8
decoders. Use A4A3 as input to a 2 4 decoder and have the four
outputs go to the enable leads of the four 3 8 decoders. The result
is that one and only one of the 32 outputs will have a value of 1.
12.13 SUM = A B C
CARRY = AB AC BC
12.14 a. The carry to the second stage is available after 20 ns; the carry
to the third stage is available 20 ns after that, and so on. When
the carry reaches the 32nd stage, another 20 ns are needed to
produce the final sum. Thus
@
T = 31 20 + 20 = 640 ns
Ap
b. Each 8-bit adder produces a sum in 30 ns and a carry in 20 ns.
Therefore,
T = 3 20 + 20 = 80 ns
lu
s st
uv
ia
@Testbanksmafia
, 12.15 a.
Characteristic table Simplified characteristic
table
Current Current Next S R Qn+1
input state state
SR Qn Qn+1
00 0 — 0 0 —
00 1 — 0 1 1
01 0 1 1 0 0
01 1 1 1 1 Qn
10 0 0
10 1 0
11 0 0
11 1 1
b.
t 0 1 2 3 4 5 6 7 8 9
S 0 1 1 1 1 1 0 1 0 1
R 1 1 0 1 0 1 1 1 0 0
Qn 0 0 1 1 1 1 0 0 — 1
12.16
@
Ap
lu
s st
uv
ia
@Testbanksmafia
