,2
,Digital Design
With an Introduction to the Verilog HDL, VHDL, and SystemVerilog
3
,Digital Design
With an Introduction to the Verilog HDL, VHDL, and SystemVerilog
Sixth Edition
M. Morris Mano
Emeritus Professor of Computer Engineering
California State University, Los Angeles
Michael D. Ciletti
Emeritus Professor of Electrical and Computer Engineering University of
Colorado at Colorado Springs
330 Hudson Street, NY NY 10013
4
,Senior Vice President Courseware Portfolio Management: Marcia J.
Horton
Director, Portfolio Management: Engineering, Computer Science &
Global Editions: Julian Partridge
Higher Ed Portfolio Management: Tracy Johnson (Dunkelberger)
Portfolio Management Assistant: Kristy Alaura
Managing Content Producer: Scott Disanno
Content Producer: Robert Engelhardt
Web Developer: Steve Wright
Rights and Permissions Manager: Ben Ferrini
Manufacturing Buyer, Higher Ed, Lake Side Communications Inc (LSC):
Maura Zaldivar-Garcia
Inventory Manager: Ann Lam
Marketing Manager: Demetrius Hall
Product Marketing Manager: Yvonne Vannatta
Marketing Assistant: Jon Bryant
Cover Designer: Marta Samsel
Cover Photo: The Mittens at Sunset – Monument Valley, Navaho Tribal
Lands, Arizona, March 2015. Photograph courtesy of M. D. Ciletti and
mdc Images LLC. Used with permission.
Full-Service Project Management: Vimala Vinayakam, SPi Global
Credits and acknowledgments borrowed from other sources and
reproduced, with permission, in this textbook appear on appropriate page
within text.
5
,© 2018, 2013, 2007, 2002 by Pearson Education, Inc., Hoboken, New
Jersey 07030. All rights reserved. Manufactured in the United States of
America. This publication is protected by Copyright, and permission
should be obtained from the publisher prior to any prohibited reproduction,
storage in a retrieval system, or transmission in any form or by any means,
electronic, mechanical, photocopying, recording, or likewise. To obtain
permission(s) to use material from this work, please submit a written
request to Pearson Education, Inc., Permissions Department, Pearson
Education, Inc., Hoboken, New Jersey 07030.
Many of the designations by manufacturers and seller to distinguish their
products are claimed as trademarks. Where those designations appear in
this book, and the publisher was aware of a trademark claim, the
designations have been printed in initial caps or all caps.
Library of Congress Cataloging-in-Publication Data
Names: Mano, M. Morris, 1927- author. | Ciletti, Michael D., author.
Title: Digital design : with an introduction to the verilog HDL, VHDL, and
system Verilog / M. Morris Mano, Emeritus Professor of Computer
Engineering, California State University, Los Angeles, Michael D.
Ciletti,
Emeritus Professor of Electrical and Computer Engineering, University
of
Colorado at Colorado Springs.
Description: Sixth edition. | Upper Saddle River, New Jersey : Pearson
Education, Inc., [2017] | Includes index.
Identifiers: LCCN 2017004488 | ISBN 9780134549897 (print : alk. paper)
Subjects: LCSH: Electronic digital computers—Circuits. | Logic circuits. |
Logic design. | Digital integrated circuits.
Classification: LCC TK7888.3 .M343 2017 | DDC 621.39/5—dc23 LC
record available at https://lccn.loc.gov/2017004488
1 17
6
,ISBN 10: 0-13-454989-9
ISBN 13: 978-0-13-454989-7
7
,Contents
1. Preface ix
1. 1 Digital Systems and Binary Numbers 1
1. 1.1 Digital Systems 1
2. 1.2 Binary Numbers 4
3. 1.3 Number-Base Conversions 6
4. 1.4 Octal and Hexadecimal Numbers 9
5. 1.5 Complements of Numbers 11
6. 1.6 Signed Binary Numbers 17
7. 1.7 Binary Codes 22
8. 1.8 Binary Storage and Registers 31
9. 1.9 Binary Logic 34
2. 2 Boolean Algebra and Logic Gates 41
1. 2.1 Introduction 42
2. 2.2 Basic Definitions 42
3. 2.3 Axiomatic Definition of Boolean Algebra 43
4. 2.4 Basic Theorems and Properties of Boolean Algebra 47
5. 2.5 Boolean Functions 50
6. 2.6 Canonical and Standard Forms 56
7. 2.7 Other Logic Operations 65
8
, 8. 2.8 Digital Logic Gates 67
9. 2.9 Integrated Circuits 73
3. 3 Gate-Level Minimization 82
1. 3.1 Introduction 83
2. 3.2 The Map Method 83
3. 3.3 Four-Variable K-Map 90
4. 3.4 Product-of-Sums Simplification 95
5. 3.5 Don’t-Care Conditions 99
6. 3.6 NAND and NOR Implementation 102
7. 3.7 Other Two-Level Implementations 110
8. 3.8 Exclusive-OR Function 115
9. 3.9 Hardware Description Languages (HDLS) 121
10. 3.10 Truth Tables in HDLS 138
4. 4 Combinational Logic 147
1. 4.1 Introduction 148
2. 4.2 Combinational Circuits 148
3. 4.3 Analysis of Combinational Circuits 149
4. 4.4 Design Procedure 153
5. 4.5 Binary Adder–Subtractor 156
6. 4.6 Decimal Adder 168
7. 4.7 Binary Multiplier 170
8. 4.8 Magnitude Comparator 172
9
, 9. 4.9 Decoders 175
10. 4.10 Encoders 179
11. 4.11 Multiplexers 182
12. 4.12 HDL Models of Combinational Circuits 189
13. 4.13 Behavioral Modeling 215
14. 4.14 Writing a Simple Testbench 223
15. 4.15 Logic Simulation 229
5. 5 Synchronous Sequential Logic 245
1. 5.1 Introduction 246
2. 5.2 Sequential Circuits 246
3. 5.3 Storage Elements: Latches 248
4. 5.4 Storage Elements: Flip-Flops 253
5. 5.5 Analysis of Clocked Sequential Circuits 261
6. 5.6 Synthesizable HDL Models of Sequential Circuits 275
7. 5.7 State Reduction and Assignment 300
8. 5.8 Design Procedure 305
6. 6 Registers and Counters 326
1. 6.1 Registers 326
2. 6.2 Shift Registers 330
3. 6.3 Ripple Counters 338
4. 6.4 Synchronous Counters 343
5. 6.5 Other Counters 351
10
,Digital Design
With an Introduction to the Verilog HDL, VHDL, and SystemVerilog
3
,Digital Design
With an Introduction to the Verilog HDL, VHDL, and SystemVerilog
Sixth Edition
M. Morris Mano
Emeritus Professor of Computer Engineering
California State University, Los Angeles
Michael D. Ciletti
Emeritus Professor of Electrical and Computer Engineering University of
Colorado at Colorado Springs
330 Hudson Street, NY NY 10013
4
,Senior Vice President Courseware Portfolio Management: Marcia J.
Horton
Director, Portfolio Management: Engineering, Computer Science &
Global Editions: Julian Partridge
Higher Ed Portfolio Management: Tracy Johnson (Dunkelberger)
Portfolio Management Assistant: Kristy Alaura
Managing Content Producer: Scott Disanno
Content Producer: Robert Engelhardt
Web Developer: Steve Wright
Rights and Permissions Manager: Ben Ferrini
Manufacturing Buyer, Higher Ed, Lake Side Communications Inc (LSC):
Maura Zaldivar-Garcia
Inventory Manager: Ann Lam
Marketing Manager: Demetrius Hall
Product Marketing Manager: Yvonne Vannatta
Marketing Assistant: Jon Bryant
Cover Designer: Marta Samsel
Cover Photo: The Mittens at Sunset – Monument Valley, Navaho Tribal
Lands, Arizona, March 2015. Photograph courtesy of M. D. Ciletti and
mdc Images LLC. Used with permission.
Full-Service Project Management: Vimala Vinayakam, SPi Global
Credits and acknowledgments borrowed from other sources and
reproduced, with permission, in this textbook appear on appropriate page
within text.
5
,© 2018, 2013, 2007, 2002 by Pearson Education, Inc., Hoboken, New
Jersey 07030. All rights reserved. Manufactured in the United States of
America. This publication is protected by Copyright, and permission
should be obtained from the publisher prior to any prohibited reproduction,
storage in a retrieval system, or transmission in any form or by any means,
electronic, mechanical, photocopying, recording, or likewise. To obtain
permission(s) to use material from this work, please submit a written
request to Pearson Education, Inc., Permissions Department, Pearson
Education, Inc., Hoboken, New Jersey 07030.
Many of the designations by manufacturers and seller to distinguish their
products are claimed as trademarks. Where those designations appear in
this book, and the publisher was aware of a trademark claim, the
designations have been printed in initial caps or all caps.
Library of Congress Cataloging-in-Publication Data
Names: Mano, M. Morris, 1927- author. | Ciletti, Michael D., author.
Title: Digital design : with an introduction to the verilog HDL, VHDL, and
system Verilog / M. Morris Mano, Emeritus Professor of Computer
Engineering, California State University, Los Angeles, Michael D.
Ciletti,
Emeritus Professor of Electrical and Computer Engineering, University
of
Colorado at Colorado Springs.
Description: Sixth edition. | Upper Saddle River, New Jersey : Pearson
Education, Inc., [2017] | Includes index.
Identifiers: LCCN 2017004488 | ISBN 9780134549897 (print : alk. paper)
Subjects: LCSH: Electronic digital computers—Circuits. | Logic circuits. |
Logic design. | Digital integrated circuits.
Classification: LCC TK7888.3 .M343 2017 | DDC 621.39/5—dc23 LC
record available at https://lccn.loc.gov/2017004488
1 17
6
,ISBN 10: 0-13-454989-9
ISBN 13: 978-0-13-454989-7
7
,Contents
1. Preface ix
1. 1 Digital Systems and Binary Numbers 1
1. 1.1 Digital Systems 1
2. 1.2 Binary Numbers 4
3. 1.3 Number-Base Conversions 6
4. 1.4 Octal and Hexadecimal Numbers 9
5. 1.5 Complements of Numbers 11
6. 1.6 Signed Binary Numbers 17
7. 1.7 Binary Codes 22
8. 1.8 Binary Storage and Registers 31
9. 1.9 Binary Logic 34
2. 2 Boolean Algebra and Logic Gates 41
1. 2.1 Introduction 42
2. 2.2 Basic Definitions 42
3. 2.3 Axiomatic Definition of Boolean Algebra 43
4. 2.4 Basic Theorems and Properties of Boolean Algebra 47
5. 2.5 Boolean Functions 50
6. 2.6 Canonical and Standard Forms 56
7. 2.7 Other Logic Operations 65
8
, 8. 2.8 Digital Logic Gates 67
9. 2.9 Integrated Circuits 73
3. 3 Gate-Level Minimization 82
1. 3.1 Introduction 83
2. 3.2 The Map Method 83
3. 3.3 Four-Variable K-Map 90
4. 3.4 Product-of-Sums Simplification 95
5. 3.5 Don’t-Care Conditions 99
6. 3.6 NAND and NOR Implementation 102
7. 3.7 Other Two-Level Implementations 110
8. 3.8 Exclusive-OR Function 115
9. 3.9 Hardware Description Languages (HDLS) 121
10. 3.10 Truth Tables in HDLS 138
4. 4 Combinational Logic 147
1. 4.1 Introduction 148
2. 4.2 Combinational Circuits 148
3. 4.3 Analysis of Combinational Circuits 149
4. 4.4 Design Procedure 153
5. 4.5 Binary Adder–Subtractor 156
6. 4.6 Decimal Adder 168
7. 4.7 Binary Multiplier 170
8. 4.8 Magnitude Comparator 172
9
, 9. 4.9 Decoders 175
10. 4.10 Encoders 179
11. 4.11 Multiplexers 182
12. 4.12 HDL Models of Combinational Circuits 189
13. 4.13 Behavioral Modeling 215
14. 4.14 Writing a Simple Testbench 223
15. 4.15 Logic Simulation 229
5. 5 Synchronous Sequential Logic 245
1. 5.1 Introduction 246
2. 5.2 Sequential Circuits 246
3. 5.3 Storage Elements: Latches 248
4. 5.4 Storage Elements: Flip-Flops 253
5. 5.5 Analysis of Clocked Sequential Circuits 261
6. 5.6 Synthesizable HDL Models of Sequential Circuits 275
7. 5.7 State Reduction and Assignment 300
8. 5.8 Design Procedure 305
6. 6 Registers and Counters 326
1. 6.1 Registers 326
2. 6.2 Shift Registers 330
3. 6.3 Ripple Counters 338
4. 6.4 Synchronous Counters 343
5. 6.5 Other Counters 351
10
