Computer Organization & Assembly
Language Programming
MIDTERM READINESS EXAM
GUIDE
Q&S
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,1. Which of the following best describes a Harvard
architecture?
- A. Single memory for instructions and data
- B. Separate memories for instructions and data
- C. Utilizes cache memory
- D. Supports virtual memory
- Correct Answer: B
- Rationale: Harvard architecture has separate storage
and buses for instructions and data, allowing simultaneous
access.
2. In the context of assembly programming, what does the
term 'operand' refer to?
- A. The operation to be performed
- B. The data on which the operation is performed
- C. The result of the operation
- D. The address of the instruction
- Correct Answer: B
- Rationale: An operand is the data that the instruction
operates on, which can be a constant value, a register, or a
memory address.
3. Which of the following ISA (Instruction Set Architecture)
features is crucial for optimizing pipelining performance?
- A. Load/Store architecture
- B. Complex Data Types
- C. Non-pipelined execution
- D. Multi-cycle instructions
- Correct Answer: A
- Rationale: A load/store architecture minimizes
dependencies that could stall the pipeline, improving
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, performance.
4. What is the purpose of a stack in assembly language?
- A. To store global variables
- B. To hold the return address and function parameters
- C. For I/O operations
- D. To maintain the instruction set
- Correct Answer: B
- Rationale: The stack is used for storing temporary
data like return addresses, function parameters, and local
variables.
5. In assembly language programming, which of the
following instructions would typically transfer control to a
different part of the program?
- A. MOV
- B. ADD
- C. JMP
- D. PUSH
- Correct Answer: C
- Rationale: The JMP (jump) instruction is used to
change the flow of execution to another instruction.
### Fill-in-the-Blank Questions
6. The _______ is the component of the CPU that fetches,
decodes, and executes instructions.
- Correct Answer: Control Unit
- Rationale: The control unit manages the execution of
instructions in the CPU by coordinating the flow of data and
operations.
7. In a typical memory hierarchy, cache memory is faster
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