ECE 385 Final Exam Questions With Verified Solutions

ECE 385 Final Exam Questions With Verified Solutions When implementing LC3 on an FPGA what component should be used to drive the CPU bus? - answerA multiplexer should be used instead of the tristate buffer depicted on the block diagram. The FPGA does not support internal tristate buffers. In what relevant case will the synthesis tool utilize a physical tristate on the FPGA? - answerWhen building a connection to external SRAM? Why do modern FPGAs not contain internal tristates? - answerTristates result in floating signals inside the chip which are bad for power and reliability reasons. What are the dimensions of the external SRAM on the DE2-115 board? - answer1Mx16 (2Mbyte) What are the SRAM UB/LB signals responsible for? - answerUpper Bit and Lower Bit control, used for read operations. What is an inherent challenge of implementing a design that uses the SRAM? - answerThe SRAM is asychronous. What is the access time for the external SRAM? - answer10ns How many cycles are needed to complete a read operation? - answer2 cycles, an additional cycle is needed since the tristate that handles the IO has an internal flip-flop for synchronization purposes. True/False: Test memory simulates SRAM perfectly, but not DRAM. - answerFalse: Test memory simulates SRAM reasonably well but not perfectly. True/False: Both read and write operations must been synchronized when dealing with external SRAM. - answerTrue What are the 3 general steps in the LC3 instruction cycle? - answer1. Fetch 2. Decode 3. Execute What actions are expected to take place during the FETCH phase? - answerState 1) MAR <- PC State 2) MDR <- M[MAR] State 3) IR <- MDR True/False: A layered test bench is advantageous because a flat test bench will allow for a a large portion of non-synthesize-able SystemVerilog. - answerFalse: Both will allow a large portion of non-synthesize-able SystemVerilog. What benefits does a layered test bench have? - answer1. Breaks down into tasks 2. Reusable 3. Modularized 4. Scalable (These all sorta come together to mean the same thing) Why might one choose to implement a flat test bench? - answerThey are well suited for unit- testing. The delay token (#) is non-synthesizable and is only intended to be used in test bench environment. What would happen if you attempted to synthesize a module containing the delay token? - answerThe compiler would simply ignore the token and compile the rest of the code as if it was not present. This could lead to unexpected behavior if you expected the delay token to actually serve some purpose. Each simulation is divided into how many queues? - answerTwo The first queue does what? - answer- All RHS of non-blocking assignments are evaluated - All RHS & LHS of blocking and continuous assignments (keyword: assign) are evaluated - Inputs and outputs are evaluated - $display and $write processed The second queue does what? - answerChange LHS of all non-blocking assignments. Essentially, the queue structure boils down to this happening last, and everything else happening prior in an unpredictable (but still defined) order. What is the proper syntax to monitor an internal signal? (This would be written in the test bench) - answeralways_comb begin: SOME_LABEL SIGNAL_NAME = MODULE.SIGNALX end What states describe the LC-3 load command? - answerstate 1) MAR <- BaseR + SEXT(offset6)