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Summary notes of GCSE OCR computing - topic: System Architecture

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This summary note provides an overview of system architecture in computing, focusing on three key concepts: the central processing unit (CPU), the fetch-decode-execute (FDE) cycle, and embedded systems. We start by explaining the role of the CPU in a computer system, including how it carries out arithmetic and logical operations, and how it interacts with memory and other components. We also discuss the different types of CPUs, including single-core, multi-core, and heterogeneous architectures. Next, we discuss the FDE cycle, which is the basic sequence of steps that a CPU uses to execute instructions. We explain how each step in the cycle works, and how they all fit together to carry out complex operations. Finally, we explore the concept of embedded systems, which are computer systems that are designed for specific purposes and are embedded in other devices, such as cars, appliances, and medical devices. We discuss the challenges of designing and programming embedded systems, including limited resources and the need for real-time performance. Throughout the summary note, we use color coding to help students identify and remember key concepts. This makes it easy for them to retrieve information and focus on the areas that are most important for their studies, whether they are preparing for GCSE or A-level exams. By the end of this summary note, students will have a clear understanding of CPU architecture, the FDE cycle, and embedded systems, which are all essential concepts in the field of system architecture in computing.

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Voorbeeld van de inhoud

System Architecture

Purpose ofthe CPK

·
The the CPI to data and instructions
purpose of is
process
Itis the
where all
searching, sorting, calculating and decision

making takes place in the
computer

The CPU will issue instructions devices
·


to other depending
the the
results
processing
on of




FDE Cycle Stages of FDE Cycl

Fetch Fetch


·
·
The value in PC is spied to the
Execute Decode MAR the
I
using address in the

MAR data/instructions are fetched
from main memory and stored in

te MDR

·
PC is incremented


Decode
scecute
E

The Instruction MDR
·

in the is

The Instruction
·
decoded the is
by control unit into
performed.
Ifthe
an
operator and
operand instruction involves a


calculation then
or
logic operation
the arithmetic unitis
logic
FDE Cycle Registers responsible for this
-




·
The Resultis stored in the

Program Counter PC accumulator


stores the
·

address of next

Memory Data (MDR)
instruction increments By I each
Register
loop of the FDE cycle
·
Holds the data/instruction
which nas been fetched
Memory Address
Register (MAR) from main memory

·
Stores the address ofthe Accumulator (ACC)
instruction to be fetched or

Holds the
·

written intermediate results
from calculation after decoding
and execution
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