WGU C952 Final Exam With Complete Solutions.

Instruction command that computer hardware understands and obeys Input writes data to memory output reads data from memory datapath performs arithmetic computations where data is transformed via computations like addition or subtraction processor control + datapath DRAM access time 50ns most expensive / GB @ $5 capacity quadrupled / year until 1990s 2 chips iPad2 consists of how many chips? 2 ARM processors A5 package has chip containing ____ ____ ____. ABI (Application Binary Interface) [the user portion of the instruction set + the OS interfaces] defines standard for binary portability across computers used by application programmers Implementation hardware that obeys the architecture abstraction secondary memory memory layer used to store programs and data between runs nonvolatile ingot The chip manufacturing process starts with a silicon ______. transistors, conductors, and insulators Blank wafers undergo 20 to 40 chemical processing steps to create (3) increases response time, decreases throughput Replacing a processor in a computer with a faster processor has what effect? (2) performance 1/execution time User CPU Time The CPU time spent in a program itself. aka CPU performance CPU execution time Also called CPU time. The actual time the CPU spends computing for a specific task. seconds for the program System CPU Time The CPU time spent in the operating system performing tasks on behalf of the program. system performance elapsed time is aka CPI (clock cycles per instruction) Average number of clock cycles per instruction for a program or program fragment algorithm Affects IC, possibly CPI in program performance IC: determines number of source program instructions executed -- number of processor instructions executed CPI: favoring slower or faster instructions programming language Affects IC, CPI in program performance IC: statements translated to processor instructions = IC deteminant CPI: features, indirect calls Compiler Affects IC, CPI IC: efficiency of it, translation speed CPI: varied Instruction Set Architecture Affects: IC, Clock Rate, CPI execution time most reliable method to evaluate performance energy most critical resource of microprocessor design LEGv8 32 registers - X0...X30, XZR - 64 bits wide memory locations - 2^62 memory doublewords {memory[0]...} -- very slow Given the importance of registers, what is the rate of increase in the number of registers in a chip over time? 63 Of a doubleword's 64 bits, what is the leftmost bit numbered? All 0s How is 0 represented in two's complement? positive In two's complement 0 is considered positive or negative? hint: leaves one less value available for the other _____s overflow When positive and negative operands are added in binary addition ___ is impossible. 11, 5, 6, 5, 5 = 32 LEGv8 field bits used L -- R = total opcode, rm (2nd reg), shamt, Rn (first reg), Rd: (destination) one in base two, multiplying by 2 is like shifting left _ place CBNZ ARM if( i==0 ) f= g + h ----------------- ____ X3, Else ADD .... B Exit Else: SUB .... Stack data structure for spilling registers organized as a last-in-first-out queue region in memory SP points to the top LR (X30) BL instruction stores return addresses in register __? LDURB, STURB read byte from source, write byte to destination used for ACSII *remember: 64-bit = doubleword = 8 bytes /0 In C, the two-letter sequence that represents null used to check whether character is the last char in string procedure In C, this must restore appropriate values before returning. MOVZ zeros the rest of the bits of the register uses 16-bit chunks, with LSL or LSR MOVK leaves the remaining bits unchanged uses 16-bit chunks, with LSL or LSR Immediate Addressing mode the operand is a constant within the instruction itself register addressing mode the operand is a register base or displacement addressing mode operand is at the memory location whose address is the sum of a register and a constant in the instruction PC-relative addressing mode the branch address is [PC + constant in instruction] primitives used to solve data race issue Linker (link editor) a systems program that combines independently assembled ML programs and resolves all undefined labels -- executable file combines the pre-compiled programs combines udef labels - ex file executable file if executed after the loader fxnl program in format of an object file that contains no unresolved references may contain: symbol tables, debugging info ("stripped executable" does not have these) sequential doubleword addresses 8 bytes apart, therefore a variable index needs to be multiplied by 8 before adding the variable to the address advance to the next address to increment a pointer to an integer (add 8 to the pointer address) code generator converts the optimized intermediate representation into a processor's machine instructions the last compiler phase type In contrast to C, Java calls the appropriate method (procedure) based on the _______ of the calling object. upper bound In contrast to C, Java explicitly stores an extra item in every array indicating the array's ____ ______. 32 ARMv8 and MIPS have __-bit instructions MIPS uses comparison instructions and branches based on the results of the comparisons GPR (General Purpose Register) type of register found in ARMv8 architecture can be used for addresses or data with virtually any instruction SSE Streaming SIMD Extesnsions introduces in 1999 version 5 2007 = 170 instructions accumulator architechture single register architecture stack architechture no registers architecture Cobol developed for use in business settings employs English vocabulary and pucntuation Fortran developed for IBMs 704 computer in 1954 one of the first widely used programming languages Algol was invented as a way to express algorithms more naturally than its predecessors Lisp Created by John McCarthy is 1958, Lisp equates programming to list manipulation. Lisp is commonly used by people working in artificial intelligence research. Short for LISt Processing. LDURB, LDURH Which LEGv8 load instructions should be generated for byte and halfword arithmetic operations? Hint: These load instructions sign extend the most significant bits, which preserves the variable's value. multiply all _____ instructions ignore overflow. normalized scientific notation a number in _________ _________ _________ does not have leading 0s adder subword parallelism takes advantage of byte- and halfword-sized data bay partitioning this to perform multiple operations in parallel combinational element an operational element, such as an AND gate or an ALU datapath element whose output values depend only on present input values state element a memory element, such as a register or a memory datapath element that has internal storage aka sequential element clocking methodology defines when signals can be read and when they can be written; timing def: the approach used to determine when data is valid and stable relative to the clock edge-triggered these state elements make simultaneous reading and writing both possible and unambiguous datapath element unit used to operate on or hold data within a processor LEGv8 implementation: include (5) the instruction and data memories, reg rile, ALU, adders dont care term an element of a logical function in which the output does not depend on the values of all the inputs RAID 0 no redundancy, widely used RAID 1 Mirroring File blocks are duplicated between physical drives High disk space utilization High redundancy Minimum of 2 drives RAID 2 Bit-level striping with dedicated Hamming-code parity. OBSOLETE. error detection and correction code RAID 3 bit-interleaving parity, network appliance multimedia, scientific codes, lg data sets protection group parity over all disks, no blocking RAID 4 Block-Interleaved Parity, network appliance for large data sets that need to be accessed in sequential blocks RAID 5 Distributed block-interleaved parity, widely used RAID 6 P+Q redundancy, recently popular striping Allocation of logically sequential blocks to separate disks to allow higher performance than a single disk can deliver. protection group the group of data disks or blocks that share a common check disk or block clock edge DRAMs enable fast access to data by transferring bits in bursts. Successive bits are transferred on each _______. flash memory writes to the same location in a __________ can wear out memory bits. direct mapped cache a cache structure in which each memory location is mapped to exactly one location in the cache write-through a scheme in which writes always update both the cache and the next lower level of the memory hierarchy, ensuring that data are always consistent between the two 1. a value is read from the cache and modified 2. modified value is written to the cache and corresponding mem loc write buffer a queue that holds data while the data are waiting to be written to memory write-back a scheme that handles writes by updating values only to the block in the cache, then writing the modified block to the lower level of the hierarchy when the block is replaced entire page what a virtual memory system writes to disk dirty bit is set when any word in a page (VM) is written and indicates if a page needs to be copied back when the page is replaced TLB (Translation Lookaside Buffer) a cache that keeps track of recently used address mappings to try to avoid an access to the page table each entry includes the physical page address, tag, and status bits fewer number of entries as a page table entry is replaced using a write-back shceme context switch A changing of the internal state of the processor to allow a different process to use the processor that includes saving the state needed to return to the currently executing process. ELR, ESR two of the special ARMv8 control registers to help with page faults, TLB misses, and exceptions.