CEA 201 EXAM QUESTIONS AND CORRECT
ANSWERS
Question 1
There is a tremendous variety of products, from single-chip microcomputers costing a
few dollars to supercomputers costing tens of millions of dollars that can rightly claim
the name "computer".
(T/F)
Correct Answer
T
Question 2
Which of the following interrelated factors go into determining the use of the
addressing bits?
A. number of operands
B. number of register sets
C. address range
D. all of the above
Correct Answer
D
Question 3
QN=9 With _________ encoding one field is used to determine the interpretation of
another field.
a. resource
b. indirect
c. direct
d. functional
Correct Answer
B
Page 1 of 152
,Question 4
The sequence of instruction cycles are always the same as the written sequence of
instructions that make up the program.
Correct Answer
F
Question 5
Which stage is required for load and store operations?
A. I
B. E
C. D
D. all of the above
Correct Answer
D
Question 6
Secondary memory is used to store program and data files and is usually visible to the
programmer only in terms of individual bytes or words.
(T/F)
Correct Answer
F
Question 7
A _________ is a mechanism that provides for communication among CPU, main
memory, and I/O.
A. System interconnection
B. CPU interconnection
C. Peripheral
D. Processor
Correct Answer
A
Page 2 of 152
,Question 8
Backward compatible means that the programs written for the older machines can be
executed on the new machine.
(T/F)
Correct Answer
T
Question 9
_________ are included in IEEE 754 to handle cases of exponent underflow.
a. Subnormal numbers
b. Guard bits
c. Normal numbers
d. Radix points
Correct Answer
Subnormal numbers
Question 10
SPARC refers to an architecture defined by ________.
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM
Correct Answer
C
Question 11
QN=4 When a microinstruction is read from the control memory it is transferred to a
_________.
a. control buffer register
b. control memory
c. control address register
d. control unit
Correct Answer
A
Page 3 of 152
, Question 12
Because all devices on a synchronous bus are tied to a fixed clock rate, the system
cannot take advantage of advances in device performance.
(T/F)
Correct Answer
T
Question 13
__________ is a design principle employed in designing the PDP-10 instruction set.
A. Orthogonality
B. Completeness
C. Direct addressing
D. All of the above
Correct Answer
D
Question 14
An advantage of using a shared L2 cache on the chip is that data shared by multiple
cores is not replicated at the shared cache level.
(T/F)
Correct Answer
T
Question 15
Both sequential access and direct access involve a shared read-write mechanism.
(T/F)
Correct Answer
T
Page 4 of 152
ANSWERS
Question 1
There is a tremendous variety of products, from single-chip microcomputers costing a
few dollars to supercomputers costing tens of millions of dollars that can rightly claim
the name "computer".
(T/F)
Correct Answer
T
Question 2
Which of the following interrelated factors go into determining the use of the
addressing bits?
A. number of operands
B. number of register sets
C. address range
D. all of the above
Correct Answer
D
Question 3
QN=9 With _________ encoding one field is used to determine the interpretation of
another field.
a. resource
b. indirect
c. direct
d. functional
Correct Answer
B
Page 1 of 152
,Question 4
The sequence of instruction cycles are always the same as the written sequence of
instructions that make up the program.
Correct Answer
F
Question 5
Which stage is required for load and store operations?
A. I
B. E
C. D
D. all of the above
Correct Answer
D
Question 6
Secondary memory is used to store program and data files and is usually visible to the
programmer only in terms of individual bytes or words.
(T/F)
Correct Answer
F
Question 7
A _________ is a mechanism that provides for communication among CPU, main
memory, and I/O.
A. System interconnection
B. CPU interconnection
C. Peripheral
D. Processor
Correct Answer
A
Page 2 of 152
,Question 8
Backward compatible means that the programs written for the older machines can be
executed on the new machine.
(T/F)
Correct Answer
T
Question 9
_________ are included in IEEE 754 to handle cases of exponent underflow.
a. Subnormal numbers
b. Guard bits
c. Normal numbers
d. Radix points
Correct Answer
Subnormal numbers
Question 10
SPARC refers to an architecture defined by ________.
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM
Correct Answer
C
Question 11
QN=4 When a microinstruction is read from the control memory it is transferred to a
_________.
a. control buffer register
b. control memory
c. control address register
d. control unit
Correct Answer
A
Page 3 of 152
, Question 12
Because all devices on a synchronous bus are tied to a fixed clock rate, the system
cannot take advantage of advances in device performance.
(T/F)
Correct Answer
T
Question 13
__________ is a design principle employed in designing the PDP-10 instruction set.
A. Orthogonality
B. Completeness
C. Direct addressing
D. All of the above
Correct Answer
D
Question 14
An advantage of using a shared L2 cache on the chip is that data shared by multiple
cores is not replicated at the shared cache level.
(T/F)
Correct Answer
T
Question 15
Both sequential access and direct access involve a shared read-write mechanism.
(T/F)
Correct Answer
T
Page 4 of 152
