CEA 201 CHAPTER 3 EXAM QUESTIONS ANSWERED CORRECTLY LATEST UPDATE 2026

CEA 201 CHAPTER 3 EXAM QUESTIONS ANSWERED CORRECTLY LATEST UPDATE 2026 John von Neumann - Answers Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton a. John Mauchly b. John von Neumann c. Herman Hollerith d. John Eckert all of the above - Answers The von Neumann architecture is based on which concept? a. data and instructions are stored in a single read-write memory b. the contents of this memory are addressable by location c. execution occurs in a sequential fashion d. all of the above software - Answers A sequence of codes or instructions is called __________. a. software b. memory c. an interconnect d. a register instruction - Answers The processing required for a single instruction is called a(n) __________ cycle. a. execute b. fetch c. instruction d. packet b. hardware failure interrupt - Answers A(n)_____________ is generated by a failure such as power failure or memory parity error a. I/O interrupt b. hardware failure interrupt c. timer interrupt d. program interrupt c. program interrupt - Answers A(n) ________ is generated by some condition that occurs as a result of an instruction execution. a. timer interrupt b. I/O interrupt c. program interrupt d. hardware failure interrupt all of the above - Answers The interconnection structure must support which transfer? a. memory to processor b. processor to memory c. I/O to or from memory d. all of the above system bus - Answers A bus that connects major computer components (processor, memory, I/O) is called a _________. a. system bus b. address bus c. data bus d. control bus address lines - Answers The __________ are used to designate the source or destination of the data on the data bus. a. system lines b. data lines c. control lines d. address lines data bus - Answers The data lines provide a path for moving data among system modules and are collectively called the_________ a. control bus b. address bus c. data bus d. system bus Processor bus - Answers The internal components of the processor are connected by _______ a. Process intra-connectivity circuitry b. Processor bus c. Memory bus d. Rambus protocol - Answers A _________ is the high-level set of rules for exchanging packets of data between devices. a. bus b. protocol c. packet d. QPI lane - Answers Each data path consists of a pair of wires (referred to as a ________) that transmits data one bit at a time. a. lane b. path c. line d. bus interface - Answers The device which is used to connect a peripheral to a bus is called ________ a. Control Register b. Interface c. Communication Protocol d. None of the above transaction layer - Answers The ____________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. a. transaction layer b. root layer c. configuration layer d. transport layer all of the above - Answers The TL supports which of the following address spaces? a. memory b. I/O c. message d. all of the above routing - Answers The QPI ____________ layer is used to determine the course that a packet will traverse across the available system interconnects. a. link b. protocol c. routing d. physical MAR - Answers Which of the following registers connects to the memory through the address bus? a. I/O AR b. I/O BR c. MAR d. MBR instruction cycle - Answers The time required to fetch an instruction from memory and execute it is called ........ a. Fetch Cycle b. Execution Cycle c. Load Cycle d. Instruction Cycle Fetch-Execute Cycle - Answers The CPU of a computer takes instructions from memory and executes them. This process is called ___________ a. Load b. Time Sequence c. Execution d. Fetch-Execute Cycle PC - Answers In the process of executing a program, which of the following are initialized first? a. MAR b. MBR c. IR d. PC IR - Answers The decoded instruction is stored in _______ a. IR b. PC c. Registers d. MDR